We characterize single- and two-qubit operations in a SiGe quantum dot array, from the perspective of its quantum information processing capabilities. The analysis includes rigorous randomized benchmarking of single- and two-qubit gates, state preparation and measurement characterization, and Bell's state tomography, which are all basic functionalities required for universal quantum computation. To assess compatibility with integrated cryogenic electronics, we evaluate qubit performance at 350, 500, and 750 mK, with high-fidelity single and two qubit operations. The highest temperature, 750 mK, falls within the realistic thermal budget for practical integrated cryogenic electronics and represents the highest operating temperature reported for this qubit platform.

The computational power and fault tolerance of future large-scale quantum processors derive in large part from the connectivity between the qubits. One approach to increase connectivity is to engineer qubit-qubit interactions at a distance. Alternatively, the connectivity can be increased by physically displacing the qubits. For semiconductor spin qubits, several studies have investigated spin coherent shuttling of individual electrons, but high-fidelity transport over extended distances remains to be demonstrated. Here we report shuttling of an electron inside an isotopically purified Si/SiGe heterostructure using electric gate potentials. In a first set of experiments, we form static quantum dots and study how spin coherence decays during bucket-brigade shuttling, where we repeatedly move a single electron between up to five dots. Next, for conveyor-mode shuttling, we create a travelling-wave potential, formed with either one or two sets of sine waves, to transport an electron in a moving quantum dot. This method shows a spin coherence an order of magnitude better than the bucket-brigade shuttling. It allows us to displace an electron over an effective distance of 10 μm in under 200 ns while preserving the spin state with a fidelity of 99.5% on average. These results will guide future efforts to realize large-scale semiconductor quantum processors, making use of electron shuttling both within and between qubit arrays.

Confining electrons or holes in quantum dots formed in the channel of industry-standard fully depleted silicon-on-insulator CMOS structures is a promising approach to scalable qubit architectures. In this communication, we present measurement results of a commercial nanostructure fabricated using the GlobalFoundries 22FDX(TM) industrial process. We demonstrate here that quantum dots are formed in the device channel by applying a combination of a back- and gate voltages. We report our results on an effective detuning of the energy levels in the quantum dots by varying the barrier gate voltages in combination with the back-gate voltage. Given the need and importance of scaling to larger numbers of qubits, we demonstrate here the feasibility of single-electron box sensors at the edge of the quantum dot array for effective charge sensing in different operation modes – sensing charge transitions in a single- and double quantum dots forming the quantum dot array. We also report measurement results demonstrating bias triangle pair formation and precise control over coupled quantum dots with variations in the inter-dot barrier. The reported measurement results demonstrate the ability to control the formation and coupling of multiple quantum dots in a quantum dot array and to sense their charge state via a Single Electron Box sensor in a commercial process for the first time.

The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 105 cm2 V−1 s−1 and low percolation density of 6.9(1) × 1010 cm−2. These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz−1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.

Micromagnet-based electric dipole spin resonance (EDSR) offers an attractive path for the near-term scaling of dense arrays of silicon spin qubits in gate-defined quantum dots while maintaining long coherence times and high control fidelities. However, accurately controlling dense arrays of qubits using a multiplexed drive will require an understanding of the crosstalk mechanisms that may reduce operational fidelity. We identify a novel crosstalk mechanism whereby the Rabi frequency of a driven qubit is drastically changed when the drive of an adjacent qubit is turned on. These observations raise important considerations for scaling single-qubit control.

As part of the National Agenda for Quantum Technology, QuTech (TU Delft and TNO) has agreed to make quantum technology accessible to society and industry via its full-stack prototype: Quantum Inspire. This system includes two different types of programmable quantum chips: circuits made from superconducting materials (transmons), and circuits made from silicon-based materials that localize and control single-electron spins (spin qubits). Silicon-based spin qubits are a natural match to the semiconductor manufacturing community, and several industrial fabrication facilities are already producing spin-qubit chips. Here, we discuss our latest results in spin-qubit technology and highlight where the semiconducting community has opportunities to drive the field forward. Specifically, developments in the following areas would enable fabrication of more powerful spin-qubit based quantum computing devices: circuit design rules implementing cryogenic device physics models, high-fidelity gate patterning of low resistance or superconducting metals, gate-oxide defect mitigation in relevant materials, silicon-germanium heterostructure optimization, and accurate magnetic field generation from on-chip micromagnets.

Full-scale quantum computers require the integration of millions of quantum bits. The promise of leveraging industrial semiconductor manufacturing to meet this requirement has fueled the pursuit of quantum computing in silicon quantum dots. However, to date, their fabrication has relied on electron-beam lithography and, with few exceptions, on academic style lift-off processes. Although these fabrication techniques offer process flexibility, they suffer from low yield and poor uniformity. An important question is whether the processing conditions developed in the manufacturing fab environment to enable high yield, throughput, and uniformity of transistors are suitable for quantum dot arrays and do not compromise the delicate qubit properties. Here, we demonstrate quantum dots hosted at a 28Si/28SiO2 interface, fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. As a result, we achieve nanoscale gate patterns with remarkable homogeneity. The quantum dots are well-behaved in the multi-electron regime, with excellent tunnel barrier control, a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance reveals relaxation times of over 1 s at 1 Tesla and coherence times of over 3 ms, matching the quality of silicon spin qubits reported to date. The feasibility of high-quality qubits made with fully-industrial techniques strongly enhances the prospects of a large-scale quantum computer

Micromagnet-based electric dipole spin resonance (EDSR) offers an attractive path for the near-term scaling of dense arrays of silicon spin qubits in gate-defined quantum dots while maintaining long coherence times and high control fidelities. However, accurately controlling dense arrays of qubits using a multiplexed drive will require an understanding of the crosstalk mechanisms that may reduce operational fidelity. We identify a novel crosstalk mechanism whereby the Rabi frequency of a driven qubit is drastically changed when the drive of an adjacent qubit is turned on. These observations raise important considerations for scaling single-qubit control.

High-fidelity control of quantum bits is paramount for the reliable execution of quantum algorithms and for achieving fault-tolerance, the ability to correct errors faster than they occur. The central requirement for fault-tolerance is expressed in terms of an error threshold. Whereas the actual threshold depends on many details, a common target is the ~1% error threshold of the well-known surface code. Reaching two-qubit gate fidelities above 99% has been a long-standing major goal for semiconductor spin qubits. These qubits are well positioned for scaling as they can leverage advanced semiconductor technology. Here we report a spin-based quantum processor in silicon with single- and two-qubit gate fidelities all above 99.5%, extracted from gate set tomography. The average single-qubit gate fidelities remain above 99% when including crosstalk and idling errors on the neighboring qubit. Utilizing this high-fidelity gate set, we execute the demanding task of calculating molecular ground state energies using a variational quantum eigensolver algorithm. Now that the 99% barrier for the two-qubit gate fidelity has been surpassed, semiconductor qubits have gained credibility as a leading platform, not only for scaling but also for high-fidelity control.

Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting.

RF reflectometry offers a fast and sensitive method for charge sensing and spin readout in gated quantum dots. We focus in this work on the implementation of RF readout in accumulation-mode gate-defined quantum dots, where the large parasitic capacitance poses a challenge. We describe and test two methods for mitigating the effect of the parasitic capacitance, one by on-chip modifications and a second by off-chip changes. We demonstrate that these methods enable high-performance charge readout in Si/SiGe quantum dots, achieving a fidelity of 99.9% for a measurement time of 1 $\mu$s.

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the 'wiring bottleneck'3-6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7-9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch-Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.

Brian Paquelet Wuetz,1, ∗ Merritt P. Losert,2, ∗ Sebastian Koelling,3, ∗ Lucas E.A. Stehouwer,1 Anne-Marije J. Zwerver,1 Stephan G. J. Philips,1 Mateusz T. Mądzik,1 Xiao Xue,1 Guoji Zheng,1 Mario Lodari,1 Sergey V. Amitonov,1 Nodar Samkharadze,4 Amir Sammak,4 Lieven M. K. Vandersypen,1 Rajib Rahman,5 Susan N. Coppersmith,5 Oussama Moutanabbir,3 Mark Friesen,2 and Giordano Scappucci1, † 1QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands 2University of Wisconsin-Madison, Madison, WI 53706 USA 3Department of Engineering Physics, École Polytechnique de Montréal, Montréal, Case Postale 6079, Succursale Centre-Ville, Montréal, Québec, Canada H3C 3A7 4QuTech and Netherlands Organisation for Applied Scientific Research (TNO), Delft, The Netherlands. 5University of New South Wales, Sydney, Australia (Dated: December 20, 2021)

Circuit quantum electrodynamics (QED) employs superconducting microwave resonators as quantum buses. In circuit QED with semiconductor quantum-dot-based qubits, increasing the resonator impedance is desirable as it enhances the coupling to the typically small charge dipole moment of these qubits. However, the gate electrodes necessary to form quantum dots in the vicinity of a resonator inadvertently lead to a parasitic port through which microwave photons can leak, thereby reducing the quality factor of the resonator. This is particularly the case for high-impedance resonators, as the ratio of their total capacitance over the parasitic port capacitance is smaller, leading to larger microwave leakage than for 50-Omega resonators. Here, we introduce an implementation of on-chip filters to suppress the microwave leakage. The filters comprise a high-kinetic-inductance nanowire inductor and a thin-film capacitor. The filter has a small footprint and can be placed close to the resonator, confining microwaves to a small area of the chip. The inductance and capacitance of the filter elements can be varied over a wider range of values than their typical spiral inductor and interdigitated capacitor counterparts. We demonstrate that the total linewidth of a 6.4 GHz and approximately 3-k Omega resonator can be improved down to 540 kHz using these filters.

Solid-state qubits integrated on semiconductor substrates currently require at least one wire from every qubit to the control electronics, leading to a so-called wiring bottleneck for scaling. Demultiplexing via on-chip circuitry offers an effective strategy to overcome this bottleneck. In the case of gate-defined quantum dot arrays, specific static voltages need to be applied to many gates simultaneously to realize electron confinement. When a charge-locking structure is placed between the quantum device and the demultiplexer, the voltage can be maintained locally. In this study, we implement a switched-capacitor circuit for charge-locking and use it to float the plunger gate of a single quantum dot. Parallel plate capacitors, transistors and quantum dot devices are monolithically fabricated on a Si/SiGe-based substrate to avoid complex off-chip routing. We experimentally study the effects of the capacitor and transistor size on the voltage accuracy of the floating node. Furthermore, we demonstrate that the electrochemical potential of the quantum dot can follow a 100 Hz pulse signal while the dot is partially floating, which is essential for applying this strategy in qubit experiments.

Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.

The mission of QuTech is to bring quantum technology to industry and society by translating fundamental scientific research into applied research. To this end we are developing Quantum Inspire (QI), a full-stack quantum computer prototype for future co-development and collaborative R&D in quantum computing. A prerelease of this prototype system is already offering the public cloud-based access to QuTech technologies such as a programmable quantum computer simulator (with up to 31 qubits) and tutorials and user background knowledge on quantum information science (www.quantum-inspire.com). Access to a programmable CMOS-compatible Silicon spin qubit-based quantum processor will be provided in the next deployment phase. The first generation of QI’s quantum processors consists of a double quantum dot hosted in an in-house grown SiGe/28Si/SiGe heterostructure, and defined with a single layer of Al gates. Here we give an overview of important aspects of the QI full-stack. We illustrate QI’s modular system architecture and we will touch on parts of the manufacturing and electrical characterization of its first generation two spin qubit quantum processor unit. We close with a section on QI’s qubit calibration framework. The definition of a single qubit Pauli X gate is chosen as concrete example of the matching of an experiment to a component of the circuit model for quantum computation.