The main concern for the commercialization of directed self-assembly (DSA) for semiconductor manufacturing continues to be the uncertainty in capability and control of defect density. Our research investigates the defect densities of various DSA process applications in the context of a 300mm wafer fab cleanroom environment; this paper expands substantially on the previously published DSA defectivity study(1) by reporting a defect density process window relative to chemical epitaxial pre-pattern registration lines; as well as investigated DSA based contact hole shrinking and report critical dimension statistics for the phase separated polymers before and after etch, along with positional accuracy measurements and missing via defect density.

EUV mask metrology and inspection challenges as well as EUV patterned wafer metrology and inspection strategies must be addressed to enable EUV patterning for pilot and high volume production. In this work we present a defectivity analysis of defects from post EUV lithography and etch and the correlation between them on 40nm and 28nm half pitch (HP) line/space structures. The objective of the work was to study the lithography and etch process window vs. pitch as well as to characterize the performance of a DUV brightfield wafer inspection system on EUV stacks in order to detect EUV related DOI's. In addition to defect characterization for the lithography and etch layers, we present the results of scattering simulation from these layers, with polarized 266nm DUV illumination, to provide insight on the light-pattern interaction and on the critical detection parameters.

Extreme ultraviolet (EUV) lithography is considered as the leading patterning technology beyond the ArF-based optical lithography, addressing the need for transistor densification to meet Moore's Law. Theoretically, EUV lithography at 13.5nm wavelength meets the resolution requirements for 1xnm technology nodes. However, there are several major challenges in the development of EUV lithography for mass production of advanced CMOS devices. These include the development of high power EUV light sources, EUV optics, EUV masks, EUV resists, overlay accuracy, and metrology and inspection capabilities. In particular, it is necessary to ensure that effective defect control schemes will be made available to reduce the EUV lithography defectivity to acceptable levels.This paper presents a study on the wafer defectivity and characterization of patterned EUV resists, with the objective of providing a quantitative comparison between the defectivity of different resist materials and different stacks. Patterned wafers were printed using the ASML (R) EUV full-field Alpha-Demo Tool (ADT 0.25 NA) at imec. The EUV resist patterns were 32nm line/spaces. Several advanced resist types were screened experimentally. The different resist types and stacks were inspected using a DUV laser based brightfield inspection tool, followed by a SEM defect review and CD metrology measurements. The patterns were characterized in terms of defect types and defect density.We identified the major defect types and discuss factors that affect the defectivity level and pattern quality, such as resist type, exposure dose and focus. Defect scattering analysis of DUV polarized light at different polarizations was performed, to indicate on the inspection performance trends for a variety of defect types and sizes of the different resists and stacks. The scattering analysis shows that higher defect scattering is induced using polarized light.

Spacer self-aligned double-patterning (SADP) offers a patterning solution to alleviate the dependency on mask1 and mask2 overlay accuracy in the litho-etch litho-etch (LELE) double-patterning scheme. However, the SADP process sequence introduces additional challenges in defect detection and hence higher risk to production yield. In this work, we developed a methodology to systematically trace the sources of SADP patterning defects by scanning the wafers through consecutive process steps, followed by SEM defect review to identify the major defect types at each step. SEM review was performed at each defect location during the process, and a defect library was established for each step. Our approach and results can be used to develop the inspection strategy during process development and create a defect library to support SADP defect monitoring in production.

We describe an electro-optical method of deciphering a watermark from a recently invented encoded image termed a concealogram. The watermark is revealed as a result of spatial correlation between two concealograms, one containing the watermark and the other containing the deciphering key. The two are placed side by side on the input plane of a modified joint-transform correlator. When the input plane is illuminated by a plane wave, the watermark image is reconstructed on part of the correlator's output plane. The key function deciphers the concealed watermark from the visible picture only when the two specific concealograms are matched. To illustrate the system's performance, both simulation and experimental results are presented.