A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with ten existing state-of-the-art FAs to validate its performance. Simulations were conducted using Cadence Computer Aided Design (CAD) tool in 45 nm CMOS process. The proposed design shows significant performance improvement in terms of speed and Power Delay Product (PDP). To evaluate performance parameters in large structures, the FAs have been cascaded and extended up to 32 bits. The proposed design, along with five out of ten existing designs worked flawlessly when extended to 32 bits. However, the proposed design achieved the best performance parameters in large cascaded circuits. (C) 2020 Karabuk University. Publishing services by Elsevier B.V.

A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performance parameters were compared with the conventional design of carry-out bit of 4-bit CLA adder. The proposed design achieved 19.69% improvement in propagation delay over the conventional CLA design. Due to low transistor count and low dynamic power dissipation, an improvement of 75.973% was achieved in average power consumption over the conventional carry-out bit of CLA design. As a result, the obtained improvement in PDP was 79.003%. Due to enhancements in performance parameters and reduced transistor count, the proposed CLA carry-out bit is expected to have extensive impact on overall adder performance.

Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic Unit. Due to increased use of portable devices nowadays, energy efficient designs having less delay have become essential. This research introduces a new two-bit binary magnitude comparator consisting 46 transistors. To analyze performance, simulation of the proposed design has been conducted using Cadence Computer Aided Design apparatus in 90 nm Technology. To analyze design feasibility, the proposed design has been compared with the existing two-bit binary magnitude comparator design. According to simulation result, the proposed design displayed 9.865 $\mu$ W average power consumption, 0.193 ns delay and 1.904 fJ Power Delay Product which was significantly less than the existing two-bit magnitude comparator designs.

Smart Home Systems have achieved great interest in the recent years to make people’s life easier and more comfortable. Smart home system offers people to control home environment in efficient and comfortable manner. Technological advancement in recent years resulted in producing a large number of smart and sophisticated systems which promoted smart living technology. This paper presents complete analysis of various smart and intelligent home automation systems. Comparative analysis of existing smart home system has been made which provides a clear idea of the pros and cons of the existing systems. Working principle of different types of smart home systems such as Dual Tone Multi Frequency based, Global System for Mobile based, voice recognition based, Zigbee based, Bluetooth based, Internet and Wi-fi based, and Gesture based smart home systems has been studied. Comments according to different aspects and features have been made for the studied smart home systems which enable users to select suitable technology according to budget and needs.