Iterative rip-up and reroute (RR), coupled with maze routing, is a standard approach in many global and detail routers. Lacking a clear indication for which connections to modify, nets in both congested and uncongested regions are ripped up and rerouted until solution quality no longer improves. Conventional approaches can expend a great deal of effort in exploring routing changes that have no meaningful benefit. In this paper, we present a new strategic approach: the impact of potential routing changes are determined precisely prior to being implemented, resulting in rapid convergence to high quality solutions with little wasted effort. Preliminary results of our prototype tool are exceptionally promising. On recently released global routing benchmarks, the new approach obtains results comparable to the best-performing massively parallel tools, but does so using only a single processor core. Our primary contribution is a new computationally efficient approach to the RR paradigm. We also find that in many cases, pattern routing alone is sufficient, and that maze routing is not required.

For years, integrated circuit design has been a driver for algorithmic advances. The problems encountered in the design of modern circuits are often intractable -- and with exponentially increasing size. Efficient heuristics and approximations have been essential to sustaining Moore's Law growth, and now almost every aspect of the design process is heavily automated. There is, however, one notable exception: there is often substantial floor planning effort from human designers to position large macro blocks. The lack of full automation on this step has motivated the exploration of novel optimization methods, most recently with reinforcement learning. In this paper, we argue that there are multiple forces which have prevented full automation -- and a lack of algorithmic methods is not the only factor. If the time has come for automation, there are a number of "traditional'' methods that should be considered again. We focus on recursive bisection, and highlight key ideas from partitioning algorithms that have broader impact than one might expect. We also stress the importance of benchmarking as a way to determine which approaches may be most effective.

Deep learning applications are compute intensive and naturally parallel; this has spurred the development of new processor architectures tuned for the work load. In this paper, we consider structural differences between deep learning neural networks and more conventional circuits -- highlighting how this impacts strategies for mapping neural network compute kernels onto available hardware. We present an efficient mapping approach based on dynamic programming, and also a method to establish performance bounds. We also propose an architectural approach to extend the practical life time of hardware accelerators, enabling the integration of a variety of heterogenous processors into a high performance system. Experimental results using benchmarks from a recent ISPD contest are also reported.

Circuit benchmarks for VLSI physical design have been growing in size and complexity, helping the industry tackle new problems and find new approaches. In this paper, we take a look back at how benchmarking efforts have shaped the research community, consider trade-offs that have been made, and speculate on what may come next.

Integrated circuit design encompasses a wide range of intractable optimization problems. In this paper, we extend linear time hill climbing techniques from graph partitioning to address detailed placement -- this results in a new way to refine circuit designs, dramatically expands the size of practical optimization windows, and enables wire length reductions on a variety of benchmark problems. The approach is versatile and straight-forward to implement, allowing it to be applied to a wide range of problems within design automation, and beyond.

Integrated circuits and electronic systems, as well as design technologies, are evolving at a great rate -- both quantitatively and qualitatively. Major developments include new interconnects and switching devices with atomic-scale uncertainty, the depth and scale of on-chip integration, electronic system-level integration, the increasing significance of software, as well as more effective means of design entry, compilation, algorithmic optimization, numerical simulation, pre- and post-silicon design validation, and chip test. Application targets and key markets are also shifting substantially from desktop CPUs to mobile platforms to an Internet-of-Things infrastructure. In light of these changes in electronic design contexts and given EDA's significant dependence on such context, the EDA community must adapt to these changes and focus on the opportunities for research and commercial success. The CCC workshop series on Extreme-Scale Design Automation, organized with the support of ACM SIGDA, studied challenges faced by the EDA community as well as new and exciting opportunities currently available. This document represents a summary of the findings from these meetings.

Abstract—Design automation tools operate on large problems, and often take hours or days to complete a run. Visualizing design data effectively can help track bugs, highlight optimization opportunies, and give a deeper understanding of the impact of subtle algorithmic changes. In this paper, we present a small, lightweight, cross-platform C language interface to the PostScript language, designed for software developers who primarily work in C or C++. Versions of this library have been a key resource for our research group in development of a number of design automation tools. The library is available in open source at https://github.com/profmadden/pstools.

Routing for dense circuits is a major challenge for VLSI physical design. Most routing approaches rely at least partially on a "rip-up and reroute" scheme, where solution quality and run times can be impacted profoundly by the order in which nets are routed. Other routing tools rely on backtracking methods embedded in integer linear programming solvers. In this paper, we present a novel approach which avoids backtracking, and largely eliminates the routing order considerations, by constructing a large number of routings simultaneously. By keeping "options open," our approach sidesteps conflicts. Our approach is a factor of ten faster than other recent work, reduces via counts by 30% or more, and is competitive on both wire length and completion rates. The approach is simple, scalable, and adaptable to the complex constraints of modern circuit fabrication processes.

The breakdown of Dennard scaling implies radical changes in the design, integration, manufacturing and deployment of new electronic systems. These changes, along with labor-force and macro-economic trends, undermine the status quo in the semiconductor and electronic design automation (EDA) fields. Of particular concern is a fairly static and aging workforce and a decline in new students interested in these fields. Recognizing the dramatic changes afoot, a series of Computing Community Consortium (CCC) sponsored workshops have been organized to identify key steps to take, to secure the future growth of the electronics industry. This paper shares some preliminary findings from the first of these workshops emphasizing challenges in finding and preparing the next generation of electronic design professionals.

Background The identification of proteins based on analysis of tandem mass spectrometry (MS/MS) data is a valuable tool that is not fully realized because of the difficulty in carrying out automated analysis of large numbers of spectra. MS/MS spectra consist of peaks that represent each peptide fragment, usually b and y ions, with experimentally determined mass to charge ratios. Whether the strategy employed is database matching or De Novo sequencing, a major obstacle is distinguishing signal from noise. Improved ability to distinguish signal peaks of low intensity from background noise increases the likelihood of correctly identifying the peptide, as valuable information is preserved while extraneous information is not left to mislead. Results This paper introduces an automated noise filtering method based on the construction of orthogonal polynomials. By subdividing the spectrum into a variable number (3 to 11) of bins, peaks that are considered "noise" are identified at a local level. Using a De Novo sequencing algorithm that we are developing, this filtering method was applied to a published dataset of more than 3000 mass spectra and an original dataset of more than 300 spectra. The samples were peptides from purified known proteins; therefore, the solutions could be compared to the correct sequences and the peaks corresponding to b , y and other fragments of significance could be identified. The same procedure was applied using two other published filtering methods. The ratios of the number of significant peaks that were preserved relative to the total number of peaks in each spectrum were determined. In the event that filtering out too many or too few signal peaks can lead to inaccuracy in sequence determination, the percentage of amino acid residues in the correct positions relative to the total number of amino acid residues in the correct sequence was also calculated for each sequence determined. Conclusions The results show that an orthogonal polynomial-based method of distinguishing signal peaks from background in mass spectra preserves a greater portion of signal peaks than compared methods, improving accuracy in sequence determination.

In this paper we present a new de novo method to identify protein and peptide amino acid sequences from tandem mass spectrometry (MS/MS) data. Our approach uses an integer knapsack dynamic programming formulation, which allows for optimization to directly consider ions other than the typical b and y variety. Rather than acting as “noise” which obscures the sequence in question, the additional ions can be used to improve identifications, and provide greater confidence in the results. We validate our approach using raw experimental data.

Floorplacement" has attracted attention, as a placement formula- tion for designs with thousands or millions of soft macro blocks. In this paper, we investigate the "standard block" approach, where soft blocks are shaped to have uniform height, rather than a wide range of different sizes. This allows many macro blocks can be treated as standard cells, simplifying the problem to one of ordinary mixed size placement. We obtain high quality results for a suite of recent benchmarks, and also present novel legalization algorithms that are more robust than the widely-used mixed-size tetris approach.

NP-hard and NP-complete problems have long been considered fundamentally intractable, and are typically addressed with heuristics or approximations algorithms. With the shift in computing from faster serial processing to large scale parallel processing, it is perhaps time to reconsider this class of problems. In principle, these difficult problems require exponential amounts of brute-force effort to obtain optimal solutions. Through efficient pruning and the use of parallel computing resources, however, surprisingly large problems are in fact within reach. The work described here is focused on finding solutions for a wide range NP-Hard problems, and in making effective pruning techniques easily accessible.

This chapter presents work on space management, legalization, and detailed placement, the design flow steps normally falling between global placement and the start of routing. Fixed-die routing dominates the industry, but faces the problem of routing failure. Space management is also an effective way of adjusting to changes resulting from gate sizing or buffer insertion. Flow-based improvements are sometimes referred to as ripple moves; one can see chains of regions, where logic elements move in sequence through, from dense regions to sparse. A physics-based model can be used to compute particle velocities between bins with different pressures. Many groups have experimented with different legalizers, window sizes for reordering, methods to perform space allocation, and so forth. The placement examples with known optimal benchmarks contain no pads; thus, there are multiple optimal configurations, corresponding to mirroring or flipping of the design.

Routing is a key stage for VLSI physical design. Steiner tree construction is a well studied topic in design automation. There have been a number of significant theoretical advances in the past few years. The focus of this paper is on combining the speed and solution quality of a high quality Steiner heuristic with the reality of modern routing. Practical designs contain routing congestion and blockages; routing is implemented across multiple layers. Each routing layer has preferred directions, and connecting vias have significant cost. In a modern design, many trees are in competition with each other for scarce routing resources. The objective is not to simply build trees with the lowest length; they must also be low cost. We present an approach that is as fast as spanning tree construction, while accurately modeling routing costs. Our work extends an earlier Steiner tree heuristic algorithm by adding the ability to minimize the routing congestion without altering the computational complexity of the underlying algorithm. We compare our CAST algorithm with the capacitated minimum spanning tree (CMST) and the ER algorithm finding that our approach offers impressive reduction in congestion cost in average about 23.1% and 63.4%, respectively.

Current Integrated Circuits contain billions of components. This makes the VLSI Physical Design process an extremely challenging task. The growing count of components, complex objectives and constraints has demanded strong algorithmic break throughs in this area. Placement of modules is one of the most critical stages in VLSI Physical Design [57]; current placement algorithms need to be both fast and effective. Optimization of interconnect length is an important objective during placement as it is directly related to signal delay in current integrated circuits. In this dissertation, we present novel combinatorial optimization techniques for the interconnect length driven VLSI Placement problem. We first present a new fast and effective global placement algorithm [7] for today's multi-million module circuits, which is based on a combination of continuous and discrete optimization techniques; specifically, it uses nonlinear optimization in conjunction with network flows. Next, we look at the placement legalization problem; two different algorithms based on dynamic programming [5] and a greedy technique [8] are proposed. Finally, a new optimization technique called enumeration sieve is proposed, which can be applied to problems of discrete nature. Algorithms and techniques presented as part of this dissertation have produced competitive published results on a variety of benchmarks.

Pioneering Achievement Award will Commemorate 40th Anniversary of Amdahl's Law Dr. Gene Amdahl will receive a SIGDA "Pioneering Achievement" award at the ACM/SIGDA member meeting of ICCAD in San Jose, CA on Tuesday evening, 6 November. This event will be open to the public.