We introduce an inverse designed silicon 4-channel CWDM demux with mean worst insertion loss of 2-3.3 dB and mean worst crosstalk of 19-26 dB. Variability and predictability are demonstrated using a commercial CMOS process.

A beam shaping approach has been implemented to realize high-performance waveguide crossings based on cosine tapers. Devices with a compact footprint of 4.7µm×4.7µm were fabricated on the GLOBALFOUNDRIES 45 nm monolithic silicon photonics platform (45 CLO technology). Fabricated devices are found to be nearly wavelength independent (±0.035dB for 1260nm≤λ≤1360nm) with low insertion loss (∼0.2dB) and crosstalk (-35dB). The measured response of the devices is consistent with the three-dimensional finite-difference time-domain simulation results. The design stability is validated by measuring the device insertion loss on eight chips, which is found to be 0.197±0.017dB at the designed center wavelength of 1310 nm.

This paper presents a computational nanophotonic design library for gradient-based optimization called the Stanford Photonic INverse design Software (SPINS). Borrowing the concept of computational graphs, SPINS is a design framework that emphasizes flexibility and reproducible results. By factoring the inverse design process into components that can be swapped out for one another, SPINS enables inverse design practitioners to easily explore different design methodologies. Here, we present the mathematical and architectural details on how to achieve these goals, using the inverse design of a wavelength demultiplexer as a primary example. Using inverse design effectively requires understanding the “control knobs” available to the designer, and, to that end, we also discuss practical considerations and heuristics for effective use of inverse design. In particular, by running inverse design on hundreds of designs of 3D wavelength demultiplexers, this paper explores the landscape of local minima, which leads to insights on the choice of initial conditions.

There has been significant interest in imaging and focusing schemes that use evanescent waves to beat the diffraction limit, such as those employing negative refractive index materials or hyperbolic metamaterials. The fundamental issue with all such schemes is that the evanescent waves quickly decay between the imaging system and sample, leading to extremely weak field strengths. Using an entropic definition of spot size which remains well defined for arbitrary beam profiles, we derive rigorous bounds on this evanescent decay. In particular, we show that the decay length is only $w / \pi e \approx 0.12 w$, where $w$ is the spot width in the focal plane, or $\sqrt{A} / 2 e \sqrt{\pi} \approx 0.10 \sqrt{A}$, where $A$ is the spot area. Practical evanescent imaging schemes will thus most likely be limited to focal distances less than or equal to the spot width.

A beam shaping approach has been implemented to realize high-performance waveguide crossings based on cosine tapers. Devices with a compact footprint of 4.7 µm × 4.7 µm are implemented on a GLOBALFOUNDRIES monolithic silicon photonics platform. Fabricated devices are found to be nearly wavelength-independent (± 0.035 dB for 1260 nm ≤ λ ≤ 1360 nm) with low insertion loss (~ 0.2 dB) and crosstalk (< -35 dB). The measured response of the devices is consistent with simulation results obtained by 3D FDTD computations. The design stability is confirmed by measuring the device insertion loss over nine chips, which is found to be 0.197 ± 0.017 dB at the designed center wavelength of 1310 nm.

In wavelength division multiplexing (WDM) schemes, splitters must be used to combine and separate different wavelengths. Conventional splitters are fairly large with footprints in hundreds to thousands of square microns, and experimentally-demonstrated MMI-based and inverse-designed ultra-compact splitters operate with only two channels and large channel spacing ($>$100 nm). Here we inverse design and experimentally demonstrate a three-channel wavelength demultiplexer with 40 nm spacing (1500 nm, 1540 nm, and 1580 nm) with a footprint of 24.75 $\mu\mathrm{m}^2$. The splitter has a simulated peak insertion loss of -1.55 dB with under -15 dB crosstalk and a measured peak insertion loss of -2.29 dB with under -10.7 dB crosstalk.

This paper presents improvements in performance, power, and area (PPA) obtained by optimizing the gear ratio (GR) between the Gate and vertical metal layer pitches in standard cells in sub-10nm node CMOS SoC designs. Changing the GR from 1:1 to 3:2 leads to better pin accessibility, routability, and higher cell density. This in turn enables a gate pitch relaxation and associated improvements in cell delay. Implementation of 3:2 GR ultra-dense cells in an SoC CPU block results in up to 17% higher performance, 4% smaller logic size, and 8% lower dynamic power at typical PVT conditions.

We have implemented an automated nanophotonic design algorithm with fabrication constraints. This was used to demonstrate a compact 3-channel wavelength demultiplexer with a channel spacing of 40 nm, insertion loss < 2.29 dB, and under 10.7 dB crosstalk.

A major difficulty in applying computational design methods to nanophotonic devices is ensuring that the resulting designs are fabricable. Here, we describe a general inverse design algorithm for nanophotonic devices that directly incorporates fabrication constraints. To demonstrate the capabilities of our method, we designed a spatial-mode demultiplexer, wavelength demultiplexer, and directional coupler. We also designed and experimentally demonstrated a compact, broadband 1 × 3 power splitter on a silicon photonics platform. The splitter has a footprint of only 3.8 × 2.5 μ m, and is well within the design rules of a typical silicon photonics process, with a minimum radius of curvature of 100 nm. Averaged over the designed wavelength range of 1400–1700 nm, our splitter has a measured insertion loss of 0.642 ± 0.057 dB and power uniformity of 0.641 ± 0.054 dB.

As pitch scaling is becoming constrained not only by lithographic resolution limits but also by fundamental device and interconnect challenges, the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node's worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts.

A dramatic and previously overlooked interaction of parasitic absorption with strain in germanium (Ge) is demonstrated through extensive simulations and experiments. Uniaxial strain of 4-5% and biaxial strain greater than 1% are the best candidates for a room temperature Ge laser.

A silicon-compatible light source is the final missing piece for completing high-speed, low-power on-chip optical interconnects. In this paper, we present a germanium nanowire light emitter that encompasses all the aspects of potential low-threshold lasers: highly strained germanium gain medium, strain-induced pseudoheterostructure, and high-Q nanophotonic cavity. Our nanowire structure presents greatly enhanced photoluminescence into cavity modes with measured quality factors of up to 2000. By varying the dimensions of the germanium nanowire, we tune the emission wavelength over more than 400 nm with a single lithography step. We find reduced optical loss in optical cavities formed with germanium under high (>2.3%) tensile strain. Our compact, high-strain cavities open up new possibilities for low-threshold germanium-based lasers for on-chip optical interconnects.

Extensive modeling and experiments demonstrate a dramatic reduction in parasitic absorption with strain due to a previously overlooked mechanism. A special resonance at 4-5% uniaxial strain indicates that this is the optimal strain level for a room temperature Ge laser.

Using an inverse design method that explores the full design space of fabricable devices, we demonstrate a compact wavelength splitter with low insertion loss (2-4 dB), high contrast (12-17 dB), and a footprint of only 2.8 × 2.8 μm.

A major difficulty in applying computational design methods to nanophotonic devices is ensuring that the resulting designs are fabricable. Here, we describe a general inverse design algorithm for nanophotonic devices that directly incorporates fabrication constraints. To demonstrate the capabilities of our method, we designed a spatial-mode demultiplexer, wavelength demultiplexer, and directional coupler. We also designed and experimentally demonstrated a compact, broadband $1 \times 3$ power splitter on a silicon photonics platform. The splitter has a footprint of only $3.8 \times 2.5~\mathrm{\mu m}$, and is well within the design rules of a typical silicon photonics process, with a minimum radius of curvature of $100~\mathrm{nm}$. Averaged over the designed wavelength range of $1400 - 1700~\mathrm{nm}$, our splitter has a measured insertion loss of $0.642 \pm 0.057 ~\mathrm{dB}$ and power uniformity of $0.641 \pm 0.054~\mathrm{dB}$.

Using an inverse design method that explores the full design space of fabricable devices, we demonstrate a compact wavelength splitter with a footprint of only 2.8 × 2.8 m. The device has low insertion loss (2 - 4 dB), high contrast (12 - 17 dB), and is robust to fabrication imperfections.

We perform efficient second harmonic and sum frequency generation by coupling infrared transverse electric (TE) modes in (111)-GaAs photonic crystal cavities. Furthermore, we develop microresonators in 3C-SiC, applicable for efficient infrared to visible light conversion.

We present germanium microdisk optical resonators under a large biaxial tensile strain using a CMOS-compatible fabrication process. Biaxial tensile strain of ~0.7% is achieved by means of a stress concentration technique that allows the strain level to be customized by carefully selecting certain lithographic dimensions. The partial strain relaxation at the edges of a patterned germanium microdisk is compensated by depositing compressively stressed silicon nitride layer. Two-dimensional Raman spectroscopy measurements along with finite-element method simulations confirm a relatively homogeneous strain distribution within the final microdisk structure. Photoluminescence results show clear optical resonances due to whispering gallery modes which are in good agreement with finite-difference time-domain optical simulations. Our bandgap-customizable microdisks present a new route towards an efficient germanium light source for on-chip optical interconnects.