Modern high-performance computing (HPC) storage systems use heterogeneous storage technologies organized in tiers to find a compromise between capacity, performance, and cost. In these systems, prefetching is a common technique used to move the right data at the right moment from a slow to a fast tier to improve overall performance while using the costly high-performance tier only when needed. Effective prefetching requires precise knowledge of the application I/O patterns. This knowledge can be extracted through the source code, I/O tracing tools or I/O functions call stacks. State-of-the-art solutions based on the latter approach mainly focus on applications with regular I/O profiles to avoid scalability issues due to the grammar-based techniques used. In this paper, we present an approach based on I/O call stacks that models POSIX and STDIO I/O patterns for both regular and irregular applications, thanks to the use of directed graphs. We present different models usable for prefetching. Our models were used to predict the next I/O call stack on five real HPC applications with a prediction accuracy of up to 98%. Compared to the state-of-the-art Omnisc'IO, they incurred up to 120x lower model overhead (334 ns vs. 45 s on LAMMPS) and had a model size 10x to 15x smaller (463 B vs. 7 kB on LQCD).

Data access has become the central issue in the era of Big Data and IO-intensive applications. This pressure on storage systems is greater in HPC, as supercomputers and their high computing capacity to handle compute-intensive applications should not be delayed by the access to data. Burst buffers play a major role in the acceleration of data access, with their multi-tiered storage architectures featuring different technologies and performance characteristics. However, data placement and management across the tiers impacts the delivered performance. In this work, we develop a simulator that is cost-effective in computation and memory footprint, capable of being integrated between a file profiler (FiLiP) and a burst buffer (SBB) on a datanode in an industrial environment. It uses the predicted files access schemes from the history extracted by FiLiP, and simulates several data placement policies for different hardware configurations executing the predicted workload. The simulation generates hints for the burst buffer to anticipate the selection of the most appropriate data management policy. The simulator is well calibrated based on real measures and its use for three scientific reference applications allowed an increase of the hit rate by a factor of 3.31 compared to the initial placement policy for the LQCD application.

The scale of HPC clusters has increased over the past decade, eventually achieving exascale in 2022. While the shift to exascale computing meets the rising demand for processing power, it introduces challenges in energy consumption and power efficiency. Dynamic Voltage and Frequency Scaling (DVFS), is a common tool that can be used to reduce the processor's power usage. However, while the effect of DVFS during classical compute tasks has already been well-documented, its impact on I/Os has not been covered by the literature. In this paper, we offer a comprehensive investigation of the impact of DVFS on a compute node comprising two AMD EPYC Rome 7282 CPU in an HPC cluster. Our contributions include (1) a methodology to microbenchmark the performance and energy consumption impact of DVFS in an HPC system through the use of carefully selected synthetic application, (2) a set of results and analysis related to the behavior of DVFS on the tested HPC nodes, and (3) some guidelines for using DVFS on HPC applications.

Black-box auto-tuning methods have been proven to be efficient for tuning configurable computer hardware, including those encountered within the High Performance Computing (HPC) ecosystem. However, because of the shared nature of HPC clusters and the complexity of the software and hardware stacks, the measurement of the performance function can be tainted by noise during the tuning process, which can reduce and sometimes prevent the benefit of the tuning approach. A usual choice for performing the tuning in spite of these interference is to add a resampling step at each iteration to reduce uncertainty, but this approach can be time-consuming and must be done carefully. In this paper, we propose a new resampling and filtering algorithm called EVADyR (Efficient Value Aware Dynamic Resampling). Compared to the state of the art, it finds a better exploration versus exploitation trade-off by resampling only promising configuration and increases the level of confidence around the suggested solution as the tuning process advances. This algorithm was able to tune efficiently two I/O accelerators highly sensitive to interference, in two different scenarios. Compared to Standard Error Dynamic Resampling (SEDR), a state of the art noise reduction strategy, we show that EVADyR is able to reduce the distance to the optimum by 93.5% and 24.7% for the two I/O accelerators respectively, as well as speed-up the experiment duration by 45.8% and 58.1% because less iterations are needed to reach the found optimum. Our results prove the importance of using noise reduction strategies whenever tuning systems running in production.

Optimizing the I/Os is essential to avoid performance bottlenecks in High-Performance Computing. Advisory hints, such as POSIX fadvise and Lustre ladvise, are designed to improve I/O performance by allowing applications to provide the file system with additional information on their access patterns. These mechanisms are supposed to enable more efficient cache utilization and reduce I/O performance bottlenecks. However, in practice, their effectiveness depends on how individual file systems interpret these hints and on how developers use them. In this paper, we offer a comprehensive investigation of the impact of advisory hints on Lustre and GPFS parallel file systems. Our contributions include: (1) a methodology to evaluate the performance impact of such hints on these widely-used parallel file systems, (2) the introduction of a benchmark that implements this methodology, and (3) we analyze the result of our benchmark, leading to practical guidelines for application developers to improve I/O performance through proper use of those hints. Our findings demonstrate that the effect of these hints varies significantly between evaluated state-of-the-art parallel file systems and highlight the need for tailored approaches in leveraging advisory hints in order to achieve optimal I/O performance.

The growing disparity between computing speed and data access times poses a significant challenge to the management of data storage in large-scale supercomputers. To address these challenges, storage systems have evolved into hierarchical architectures with multiple levels that accommodate various hardware technologies. Each level offers a unique combination of performance, cost, and capacity. In this work, we introduce a paradigm shift in data management across the storage tiers by transitioning from block-level to file-level granularity to optimize data placement. Our online prediction model uses file characterization (input, log, checkpoint, work, and output) to predict file reuse with 97% accuracy, categorizing each file during usage and enabling proactive data management strategies. Using three real applications and a benchmark, we validate our work and demonstrate significant improvements in data hit rates, reaching 55% and 57% for LQCD and the benchmark applications, respectively. Even with lower performance improvements, our approach remains competitive with NEMO and NAMD, achieving a 3% gain over both LRU and LFU on NEMO and matching LRU performance while being 1% lower than LFU on NAMD.

The new emerging scientific workloads to be executed in the upcoming exascale supercomputers face major challenges in terms of storage, given their extreme volume of data. In particular, intelligent data placement, instrumentation, and workflow handling are central to application performance. The IO-SEA project developed multiple solutions to aid the scientific community in adressing these challenges: a Workflow Manager, a hierarchical storage management system, and a semantic API for storage. All of these major products incorporate additional minor products that support their mission. In this paper, we discuss both the roles of all these products and how they can assist the scientific community in achieving exascale performance.

Modern High Performance Computing (HPC) storage systems use heterogeneous storage technologies organized in tiers to find a compromise between capacity, performance, and cost. In these systems, prefetching is a common technique used to move the right data at the right moment from a slow to a fast tier to improve the overall performance while using the costly high-performance tier only when needed. Effective prefetching requires precise knowledge of the application I/O patterns. This knowledge can be extracted through the source code, I/O tracing tools or I/O functions call stacks. State-of-the-art solutions based on the latter approach mainly focus on applications with regular I/O profiles to avoid scalability issues due to the grammar-based techniques used. In this paper, we present an approach based on I/O call stacks that models I/O patterns for both regular and irregular applications, thanks to the use of directed graphs. We present different models for prefetching. Our models were used to predict the next I/O call stack on two real HPC applications and one synthetic workload with an accuracy of up to 98%, while keeping a low overheadt.

To become auto-adaptive, computer systems should be able to have some knowledge of incoming applications even before launching the application on the system, so that the runtime environment can be customized to the particular needs of this application. In this paper, we propose the architecture of an auto-tuner which relies on record linkage methods to match an incoming application with a database of already known applications. We then present a concrete implementation of this auto-tuner on High Performance Computing (HPC) systems, to submit unknown incoming applications with the best possible parametrization of a smart prefetch strategy by analyzing their metadata. We test this auto-tuner in conditions close to a production environment, and show an improvement of 28% compared to using the default parametrization. The conducted evaluation reveals a negligible overhead of our auto-tuner when running in production and a significant resilience for parallel use on a high-traffic HPC cluster.

SummaryHigh performance computing (HPC) applications' behaviors rely on highly configurable software environments and hardware devices. Finding their optimal parametrization is a complex task, as the size of their parametric space and the non‐linear behavior of HPC systems make hand‐tuning, theoretical modeling or exhaustive sampling unsuitable in most cases. In this article, we propose an online auto‐tuner that relies on black‐box optimization to find the optimal parametrization of input/output (I/O) accelerators for a given HPC application in a limited number of iterations, without making any assumption on the behavior of the tuned system. As many heuristics are available in the literature, we need to guarantee the quality of the tuning by selecting the most appropriate one. To do so, we provide a comparative study of the efficiency of three heuristics applied to tuning two I/O accelerators developed by the Atos company: a pure software accelerator (small read optimizer) and a mixed hardware‐software one (smart burst buffer). To select the most efficient heuristic for our use case, we define several new metrics to evaluate the quality of an auto‐tuner, in an online and offline settings. We find that genetic algorithms provide a faster convergence rate and a faster computation time but surrogate models provide a better score in terms of both distance to the optimum and trajectory stability. Overall, the obtained results show that auto‐tuning heuristics improve the execution time of applications used conjointly with both SRO and SBB accelerators.

Modern computer components, both hardware and software, come with many tunable parameters and their parametrization can have a strong impact on their performance. Auto-tuning methods relying on black-box optimization have delivered good results for finding the optimal parametrization of complex computer systems. In this paper, we present a new optimization framework, called the S mart H PC MAN ager. It provides an out-of-the-box Web application to perform black-box auto-tuning of computer components running on a distributed system for an application submitted by the user. This framework integrates three state-of-the-art heuristics, as well as resampling strategies to deal with the noise due to resource sharing, and pruning strategies to speed-up the convergence process. We demonstrate a possible use-case of this framework by tuning a software I/O accelerator.

This paper presents the main features and the programming constructs of the DCEx programming model designed for the implementation of data-centric large-scale parallel applications on Exascale computing platforms. To support scalable parallelism, the DCEx programming model employs private data structures and limits the amount of shared data among parallel threads. The basic idea of DCEx is structuring programs into data-parallel blocks to be managed by a large number of parallel threads. Parallel blocks are the units of shared- and distributed-memory parallel computation, communication, and migration in the memory/storage hierarchy. Threads execute close to data using near-data synchronization according to the PGAS model. A use case is also discussed showing the DCEx features for Exascale programming.

This paper presents a novel approach using deep neural networks in HPC software application domain. The approach uses Recurrent Neural Network (RNN) and more specifically Long Short-Term Memory (LSTM) models to classify jobs running on HPC clusters into different application families. This is a mandatory step in order to optimize their run time environment for our future work. Our approach was inspired by the recent advancement in Deep Learning in the AI area. We implemented our models on a HPC cluster and took advantage of the GPU to accelerate the training process. The evaluation of our models on a database of synthetic jobs (with more than 500 runs) gave good results for the classification of short duration jobs (less than 1 hour). In comparison with the conventional approaches such as Support Vector Machine and Hidden Markov Model, the stateful LSTM implementation improves significantly the classification accuracy for long duration jobs (more than 2 hours).

The integration of local storage technologies alongside traditional parallel file systems on HPC clusters, is expected to rise the programming complexity on scientific applications aiming to take advantage of the increased-level of heterogeneity. In this work, we present uMMAP-IO, a user-level memory-mapped I/O implementation that simplifies data management on multi-tier storage subsystems. Compared to the memory-mapped I/O mechanism of the OS, our approach features per-allocation configurable settings (e.g., segment size) and transparently enables access to a diverse range of memory and storage technologies, such as the burst buffer I/O accelerators. Preliminary results indicate that uMMAP-IO provides at least 5-10x better performance on representative workloads in comparison with the standard memory-mapped I/O of the OS, and approximately 20-50% degradation on average compared to using conventional memory allocations without storage support up to 8192 processes.