Self-aligned via (SAV) schemes are commonly used for back-end-of-line (BEOL) interconnect structures that have scaled to <; 90nm BEOL pitch [1]. In one implementation of this scheme, a TiN metal hard mask (MHM) is used for trench pattern definition, while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process using RF pulsing in a capacitively coupled etch reactor that provides a solution to both via distortion / striation and critical dimension (CD) bias loading. Electrical results will be discussed.

Back-end-of line (BEOL) interconnect scaling has led to the implementation of self-aligned via (SAV) schemes for ≤ 90 nm BEOL pitches [1]. In one implementation of this scheme, a TiN metal hardmask (MHM) is used for the trench pattern definition while the interconnect vias are patterned using a tri-layer resist mask such that the vias are self-aligned to the underlayer trench lines [2]. In this work, we describe a SAV etch process that enables the use of thin (≤ 15 nm) TiN MHM. Key attributes of the via and trench etching process in a capacitively coupled etch reactor are described to meet physical performance requirements and eliminate tradeoffs between via chain yield and via-to-metal (M2-V1) bridging. Low-k sidewall damage, post-etch wet clean, and metallization are discussed. Finally, the physical etch performance is correlated to the device breakdown voltage (VBD) and time-dependent dielectric breakdown (TDDB) lifetime performance.