This work provides a comprehensive performance analysis of Core Embedded Insulator Nanosheet Field Effect Transistors (C-NSFET) with pocket implant. As transistor scaling advances into sub-5nm nodes, NSFETs are a strong candidate to lessen short channel effects. Additionally, the CNSFETS has demonstrated enhanced performance in terms of reduced off current, which results in a superior Ion/Ioff ratio. Pocket engineering has also become a crucial method for boosting carrier transport, lowering leakage, and increasing short-channel management. Using Silvaco TCAD simulator, critical DC metrics such as threshold voltage, Ion and Ioff current are examined in connection to pocket doping profiles and geometries for C-NSFET. The device's suitability for linear and high-frequency applications is assessed using analog and RF metrics such as transconductance (gm), higher-order transconductance derivatives (gm2, gm3), VIP2, VIP3, IIP3, IMD3 and parasitic capacitances (Cgs and Cgd). The optimized pocket design significantly improves drive capacity and linearity, which makes them appealing options for future nanosheetbased CMOS devices intended for RF and mixed-signal applications. The pocket-engineered NSFET under consideration has a significant performance advantage over the traditional structure of NSFET. With an enhanced Ion/Ioff ratio of 1.52 x 105, the device achieves an ON-state drain current of 7.15 x 10-5 A. and an OFF-state current of 4.71 x 10-10 A. The effectiveness of pocket engineering for low-power applications is demonstrated by the suggested device's 28.6 % increased Ion/Ioff ratio and 40.7 % enhanced ON-current over the traditional NSFET.

This work proposes and analyzes a novel Extended Source F-type Nano Field-Effect Transistor (ES-F-NFET). The device features a low bandgap Si_0.45Ge_0.55 source extended toward the drain, which is confined using a wide bandgap material (e.g., SiC) to suppress OFF-state leakage. Device simulations use the Schrodinger–Poisson approach with NEGF for quantum transport. Various Wide Band Gap Materials (WBGm) are evaluated at the drain to study I_DS-V_gs characteristics, supported by energy band diagrams, transmission probabilities, and density of states. Along with this, analog/RF performance is assessed through transconductance (g_m), cut-off frequency (f_t), and capacitance metrics. Linearity and reliability are further evaluated using higher-order transconductance (g_m3,g_m2), distortion levels, intercept points (IIP_3,VIP_2,VIP_3), 1-dB compression and IMD_3. The ES-F-NFET with Si_0.45Ge_0.55 and SiC as confining material shows superior performance for GaAs-based counterparts at the drain compared to β-Ga_2O_3, SiC, and GaN due to better confinement at the interface and wider bandgap.

Biosensors are a common phenomenon now a days and used for various medical applications. So, they are required to be more sensitive and reliable. Tunnel Field Effect Transistor are now a days used for these applications and have replaced MOS- FETs because they offer high ratio of OFF to ON current (IOFF, ION), faster switching times, improved sub-threshold swing (SS), thereby low leakage current and low power consumption. A proposed DG-JL-TFET (Dual-Gate Junctionless TFET) structure is presented for biosensing application. A nanocavity is made in the gates where the biomolecules with different permittivity can be filed. These different permittivity’s represent biomolecules with different dielectric constants. Where the tunnelling is visible in the ON state, the energy band diagrams for the OFF and ON states are displayed. Tunnelling facilitates current flow even at lower voltages, and it yields drain current at varying gate voltage values. The graphs of ratio of ION to IOFF current are plotted. The values of threshold sensitivity, drain cur-rent sensitivity are calculated for various biomolecules.

This chapter examines 6T, 8T, and 10T SRAM cell designs and their compatibility with 45nm, 90nm, and 180nm technological nodes. It primarily examines the power consumption, speed, and signal strength of SRAM cell designs. The study uses tools to see how each SRAM cell design works under different conditions. For read, write, and hold operations of the SRAM cell designs, it compares the signal to the noise margin. The findings aid in understanding the advantages and disadvantages of each design, using technologies such as 45nm, 90nm, and 180nm to guide future advancements in memory technology.

When semiconductor scaling gets close to the sub-5nm range, regular MOSFETs have problems because of short-channel effects (SCEs) and the basic subthreshold swing (SS) limit of 60 mV/decade. Tunnel Field-Effect Transistors (TFETs) have become a promising alternative because they use a band-to-band tunneling (BTBT) process. This paper talks about the progress of Nanotube FET (NTFET) architectures, focusing on their hollow cylindrical shape, which gives them better electrostatic control than nanowire equivalents. We look at different types of structures, such as electrostatic doping (ED) and heterojunction integration (SiGe/Si, InGaAs/InP), and how they can improve ON-state current and make ultra-steep subthreshold slopes.

This chapter focusses on a comparison of SRAM cell design with six, eight, and ten cell designs and discusses them in the context of various technology nodes, such as 45nm, 90nm, and 180nm. The emphasis is put on essential performance aspects, such as power consumption, speed, and signal quality. Through the application of complex analyzing tools, the study examines the performance of each design under the various conditions, specifically the signal-to-noise margin when performing the read, write, and hold operations. The findings are useful in indicating the strengths and weaknesses of each design, giving an insight into the possible impact of different technologies on the future of memory technology.

As technology scales into deep submicron regimes, dynamic power,leakage power, and noise susceptibility have become critical challenges in digital circuit design. The XNOR gate is a fundamental building block in arithmetic, error detection, and cryptographic circuits. This work presents detailed analysis and comparison of XNOR gate implementations using Static CMOS logic, Domino logic, and Domino logic with a keeper transistor in 90 nm technology using Cadence Virtuoso. The impact of keeper transistor sizing on propagation delay, power consumption, charge sharing is systematically analyzed. The proposed analysis provides practical design guidelines for high-speed and low-power XNOR circuits.

This work demonstrates a charge plasma-based Gate-All-Around (GAA) nanowire field-effect transistor (FET) for high-sensitivity ammonia (NH3) gas sensing. The proposed device utilizes palladium (Pd) and molybdenum (Mo) as gate metals, where Pd exhibits superior performance due to its strong catalytic interaction with NH3 molecules. The sensing mechanism is governed by adsorption-induced work function modulation at the metal-gate interface, leading to measurable changes in threshold voltage (Vth), ON-state current (ION), and OFF-state current (IOFF). A systematic work function variation from 50 to 200 meV reveals significant enhancement in sensing metrics, with the ION/IOFF ratio improving from 2.6 × 108 to 1.6 × 1011 for Pd. Furthermore, channel length scaling and dielectric engineering demonstrate improved electrostatic control, with HfO2 ( 6.3

In the recent era, the semiconductor industry, which plays a pivotal role in powering today's cutting-edge technologies, relies heavily on a broad spectrum of materials, entailing of silicon and rare earth elements. These materials serve as the backbone for crucial components, such as solar cells, transistors, IoT sensors, and the intricate circuits found in self-driving cars. Consequently, there is a notable surge in demand for these devices, marking a paradigm shift in the technological landscape. The first section of this comprehensive exploration delves deeply into semiconductor materials. Understanding their profound impact on electronic devices and the intricacies of the manufacturing process is fundamental for anyone seeking a comprehensive grasp of this dynamic industry. Moving forward, the second part focuses on the properties and physics governing semiconductor materials. The electronic conductivity of these materials is of paramount importance, and the chapter unravels the challenges involved in the efficient and cost-effective large-scale manufacturing of new materials with these crucial properties. Segment three navigates through the vast realm of semiconductor applications, shedding light on their pivotal role in various electronic devices and cutting-edge technologies. It accentuates the unique electrical properties that make semiconductors indispensable in industrial settings.In the fourth section, attention is paid to the present market scenario, where the semiconductor market stands out for its stability across diverse industrial sectors. The chapter meticulously examines the production expenses associated with different materials, ranging from the widely used silicon to the more exotic rare earth metals. Essentially, this chapter guides readers through the complex trends in the semiconductor industry, offering a concise overview of material development and influential factors. It also encourages the exploration of innovative solutions to propel the Very Large Scale Integration (VLSI) industry toward unprecedented advancements.

The chapter "Nanoelectronic Horizons" presents a forward-looking exploration of the symbiotic relationship between Field-Effect Transistor (FET) technologies and nanostructures, offering a glimpse into the future of nanoelectronics. Acknowledging the foundational role of FETs in modern electronics, this chapter unfolds the transformative potential that emerges with the integration of nanostructures. Beginning with a historical overview, the narrative traces the evolution of FET technologies, setting the stage for the contemporary landscape. The foundations of FieldEffect Transistors, including their diverse types and applications, are succinctly explained. The subsequent transition into the realm of nanostructures unveils their unique properties at the nanoscale and establishes them as enablers of advanced functionalities in electronics. The chapter delves into the synergies between FET technologies and nanostructures, emphasizing their role in pushing the boundaries of traditional electronic capabilities. Exploration of recent advancements reveals cutting-edge developments in nanostructure integration, showcasing real-world applications and breakthroughs in research. Challenges and potential solutions in merging these technologies are examined, paving the way for a deeper understanding of the intricate landscape. As the narrative unfolds, readers are guided through the potential impact on various industries, the environmental considerations, and the regulatory landscape. The chapter concludes by envisioning the future prospects of FET technologies linked to nanostructures, offering insights into market trends, technological growth areas, and the societal implications of this transformative journey. Lastly, this chapter serves as a compass guiding readers through the evolving landscape of FET technologies with nanostructures, beckoning towards a future where innovation and collaboration redefine the horizons of nanoelectronics.

As semiconductor components move beyond the 5nm node, traditional FinFET designs face increasing limitations in power efficiency and electrostatic control. Nanosheet field effect transistors (NSFETs), which offer improved electrostatic integrity, higher drive current, and lower leakage currents, have emerged as a promising substitute. This work provides a comprehensive analysis of NSFET advancements, including conventional NSFETs, stacked nanosheet FETs, and Core-Insulator Embedded NSFETs (C-NSFETs). Key performance indicators such as, on/off current ratio, maximum transconductance, manufacturing challenges, and future direction are discussed to highlight the role of NSFETs in facilitating continuous CMOS growth. This study also looks into how NSFET efficiency is affected by changes in the method, new materials, and applications in designing circuits. According to the study, C-NSFETs provide superior electrical control in comparison to conventional NSFETs; nevertheless, their widespread use needs further advancements in temperature control and variability suppression.

TFETs have garnered significant attention as a viable alternative to traditional metal-oxide-semiconductor field-effect transistors because of their capacity to below 60 mV/decade subthreshold swing, which is essential for lesser power consumption usage. This paper provides an in-depth review of the latest advances TFET technology, emphasizing innovative design approaches, material developments, and performance improvements. We delve into the fundamental physics of band-to-band tunneling mechanisms that enable TFETs to function at reduced voltages, thereby lowering power consumption. Various TFET configurations, including planar and heterojunction designs, are examined for their influence on important performance metrics such as Ion, Ioff, and threshold voltage. Additionally, we discuss the incorporation of materials like higher-k dielectrics to enhance TFET performance. In this review paper, we talk about the different design parameters, such as material other than conventional silicon for the device, the effect of higher-k dielectric materials, etc., on device performance-parameters.

In the field of Very-Large Scale Integration (VLSI), Oscillators play a very crucial role and hence are widely used across the globe. The designers in VLSI field use Ring Oscillators for Global Process Monitoring. These ring oscillators are better used if the frequency is controlled, making it of use with multiple frequencies. The frequency is thus controlled by delay manipulation which can be done by controlling supply voltage, load capacitance, control voltage, and effective width of device. These are applied in wafer testing to determine the impact of variations in the manufacturing process. Ring oscillators may also be utilized to determine the impact of voltage and temperature on a chip. A better frequency range makes the oscillators to be used in Integrated Circuits (ICs) to generate clock, PLL, signal generators, radios, television, and many more. This work presents the design and analysis of different designs of Current Starved Voltage Controlled Oscillators (CSVCOs). The study examines the impact of changing design parameters on performance parameters such as frequency, power consumption, and phase noise, jitter and output noise. Simulation results identify the trade-offs of each configuration, providing insights into the best design options for a variety of applications. We are using 7nm technology node to implement our designs in Cadence Virtuoso software.

In this work, an L-shaped Tunnel FET is demonstrated for the impact of the simulation models and temperature variations. When temperature increases above the room temperature (250K to 450K), it significantly affects the carrier mobility and carrier injection process. The SRH (Shockley-Read-Hall) and TAT (Trap-assisted Tunneling) show their significance in increasing the OFF -state current (ambipolar behavior) for the lower and negative values of gate voltage. When gate voltage rises, the BTBT model (Band-to-Band-Tunneling) starts to show its presence, and the impact of SRH and TAT models starts decreasing. Because of this, the OFF -state current starts diminishing as gate voltage increases. According to the applied electric field, the BTBT, SRH, and TAT current functionalities have particular confining regions. TAT and SRH aspects predominate drain current at weak electric fields, as they are very susceptible to temperature variations. Hence, the change in models and temperature affects the device efficacy, such as analog and high-frequency functionality, and it necessitates a detailed investigation.

In a vertical TFET structure, controllability over the gate is enhanced because of the favorable electrostatic potential and tunneling under the entire gate region by preventing the direct source to drain tunneling. For an L-shaped TFET, the Band-to-Band-Tunneling (BTBT) is perpendicular and parallel to the channel length. Also, it has a higher I on (ON-current) with suppressed ambipolar current (low I ambi ) and is more scalable than other vertical BTBT mechanism-based TFET structures. The reliability of n-type single gate L-shaped TFET (SG-nLTFET) is investigated by examining: (1) impact of temperature (Temp K ) variation (from 260 K to 460 K) and (2) Interface trap charge (ITCs) polarity at fixed charge density on analog /RF /linearity figure of merits (FOMs). The obtained results reveal that change in polarity of ITCs at the Si/HfO 2 interface,modifies the analogue characteristics of the SG-nLTFET significantly in terms of turn-on voltage as well as I on . The temperature sensitivity of SG-nLTFET device indicates that the ShockleyReadHall (SRH) and Trap-Assisted-Tunneling (TAT) phenomenon dominates at lower gate bias and degrades the I on /I off ratio at high temperatures. On the other hand, the BTBT mechanism predominates in the subthreshold regime of transfer characteristics. Furthermore, the results reveal that the off-state current (I off ) degrades dramatically at high temperatures. According to the empirical analysis, SG-nLTFET is insusceptible to Positive-ITCs (Donor trap charges, P-ITCs) present at Si/HfO 2 interface in comparison to Negative-ITCs (Acceptor trap charges, N-ITCs).

In this work, a novel ultra-thin finger-like source region-based TFET (UTS-F-TFET) is used for the implementation of a temperature sensor or resistance temperature detector (RTD). Gate and source contact metal with specific work functions are deposited to provide proper functioning and detection of temperature deviation. Lower band gap material (Silicon-Germanium, SiGe) is used as source material to compensate for the limitation of lower ON-state current in the UTS-F-TFET. Horizontal as well as vertical tunneling with reduced drain-channel interface, conductive oxide (high-k) and exposed source and gate electrode are the key factors that are used to implement the RTD. ON-state current and gate biasing are used to calculate the effective change in resistance with fixed drain bias, so ON-state current has opted as the fundamental sensing parameters. The findings of the sensing parameters aid the possibility of using the proposed device for RTD applications.