This work presents a preamplifier-based high-speed comparator design specifically developed for analog-to-digital conversion systems. The proposed architecture demonstrates significant performance enhancements, particularly in switching speed and offset cancelation, when compared to traditional preamplifier comparator implementations. The design is implemented in a 180nm CMOS technology through Cadence Virtuoso, the circuit operates with a 1.8V power supply. The simulation results show substantial performance gains, with slew rates of 8.902 kV/µs (positive) and 7.509 kV/µs (negative), along with minimized signal transition times. The design achieves a propagation delay of 33.9µs while maintaining an ultra-low power dissipation of 0.525µW.

Fast Fourier Transform is one of the most efficient methods of performing computation in Digital signal processing blocks. These computations are basically performed by the inherent floating-point multiplier units residing inside the butterfly units of any FFT. To optimise an FFT for higher efficiency and performance, it is inevitable to use highly efficient adder and multiplier units within the datapath architecture of a FFT processor. This work proposes high-performance FFT units designed using optimised Vedic multiplier units for DSP processor cores. Choice of Vedic multiplier decreases power and delay overheads of design which leads to production of an efficient FFT. A comparative analysis is presented for 24-bit Vedic multiplier using nine adder variants. A separate analysis of inherent adders is also done. Using the two best proposed Vedic multipliers, FFT units of 8, 16 and 64-point are designed respectively. The designed FFT units are compared for dynamic power, area and delay with existing designs and an analysis is presented. Power efficiency of nearly 25% and delay efficiency of around 50% is achieved with respect to the existing designs. The design is simulated on Virtex-7 FPGA using Verilog HDL.

This paper presents an Intelligent Multilevel Car Parking System Using RFID. RFID is the most advanced technology for data transfer, tracking and monitoring because of its quick data transfer rate and small size, and also along with reed sensors which makes the system efficient. In the presented paper, microcontroller 89s52 and PIC16F877 are used for the car parking system, and both these microcontrollers have been combined in the same system which leads to circuit reduction. In addition to the car parking system we have incorporated a license plate recognition system which works on OCV (open computer vision) technology and online availability of parking slots using B/S (browser and server) architecture.

The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potential power saving achievable by voltage scaling while proposed 9T cells enhance stability. Layouts are also being made to create as compact a cell as possible. The results are compared with the actual known results and have been found justified.

The requirement for maximum noise-tolerant SRAM cells with low dissipating power is increasing day-by-day. The paper presents 9T SRAM cell which targets certain stability parameters, capable of tolerating the maximum noise with low dissipating power. 9T SRAM is an isolated SRAM with two separate read ports that help in enhancing the stability parameters. This is done at 1 V using a 45 nm technology node. For simulation and analysis of stability parameters, Cadence Virtuoso and EDA tanner tools are used. The work is also compared with previous works of various 6T, 7T and 8T SRAM cells.

In this paper, a system for filtering event-related potentials/electroencephalograph is exhibited by adaptive noise canceller through an optimization algorithm, oppositional hybrid whale-grey wolf optimization algorithm (OWGWA). The OWGWA can choose the control parameters of the grey wolf algorithm utilizing whale parameters. To balance out the randomness of optimization strategies another methodology is implemented called controlled search space. Adaptive filter's noise reduction capability has been tested through adding adaptive white Gaussian noise over contaminated EEG signals at different noise levels. The performance of the proposed OWGWA-CSS algorithm is evaluated by signal to noise ratio in dB, mean value, and the relationship between resultant and input ERP. In this work, ANCs are also implemented by utilizing other optimization techniques. In average cases of noisy environment, comparative analysis shows that the proposed OWGWA-CSS technique provides higher SNR value, significantly lower mean and higher correlation as compared to other techniques.

The paper presents a new and modified area and power efficient carry select adder is proposed using Weinberger architecture and it is compared for efficiency with modified Carry Select Adder using Han Carlson, Brent Krung, and Ling adder architectures along with conventional carry select adder. Carry Select Adder proposed here using Weinberger architecture turned out to be the best in terms of area and power. Simulations of all five adder architectures are performed in Xilinx Vivado tool version 14.4 and hardware implementations are performed on zynq 7000 FPGA board which uses 28nm technology.

This paper presents the C code optimization of Oppositional Whale Grey Wolf Algorithm with Control Search Space (OWGWA-CSS) used for denoising EEG signal for its real-time implementation on floating point DSP processor TMS320C6713. In general, developers tried to speed up the program all-time which leads to increase in the code size so as increase the complexity as well as difficult readability. To make the code efficient it is important to optimize the C code. For optimizing the C code first, the MATLAB code is converted to C and then implemented on DSP processor. Here, multiple C code optimization techniques for the efficient implementation of OWGWA-CSS algorithm on DSP processor TMS320C6713 is presented. The aim of optimizing C code is to reduce the computational burden and speed up the process. The work done here is a step to minimize Millions Instruction Per Second (MIPS) used to execute the c- code of OWGWA-CSS EEG noise cancellation algorithm. The C code optimization is done by using Code Composer Studio (Integrated Development environment for TMS320C67xx series). CCS is used for optimization, profiling, debugging and implementation. After applying various C code optimization techniques 25% reduction in MIPS has been obtained.

In this paper, the Oppositional Whale Optimization Algorithm (OWOA) is applied to Adaptive Noise Canceller (ANC) for the filtering of Electroencephalography/Event-Related Potentials (EEG/ERP) signals. Performance of ANC will be improved by calculating the optimal weight value and proposed OWOA technique is used to update weight value. Adaptive filter’s noise reduction capability has been tested through consideration of White Gaussian Noise (WGN) over contaminated EEG signals at various SNR levels ([Formula: see text]10[Formula: see text]dB, [Formula: see text]15[Formula: see text]dB and [Formula: see text]20[Formula: see text]dB). The performance of the proposed OWOA algorithm is assessed in terms of Signal to Noise Ratio (SNR) in dB, mean value, and the correlation between resultant and input ERP. In this work, ANCs are also implemented by utilizing conventional gradient-based techniques like Recursive Least Square (RLS), Least Mean Square (LMS) and other optimization algorithms such as Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and WOA techniques. In average cases of noisy environment, comparative analysis shows that the proposed OWOA technique provides higher SNR value and significantly lower mean, and correlation as compared to gradient-based and swarm-based techniques. The comparative results show that extracting the desired EEG component is more effective in the proposed OWOA method. So, it has seen that OWOA-based noise reduction technique removing the artifacts and improving the quality of EEG signals significantly for biomedical analysis.

This paper presents the reduction of baseline wander noise found in ECG signals. The reduction has been done using wavelet transform inspired error normalized step size least mean square (ENSS-LMS) algorithm. We are presenting a wavelet decomposition-based filtering technique to minimize the computational complexity along with the good quality of output signal. The MATLAB simulation results validate the good noise rejection in output signal by analyzing parameters, excess mean square error (EMSE) and misadjustment.

This paper presents an optimization algorithm for Adaptive Noise Canceller by taking Electroencephalography/Event-Related Potentials (EEG/ERP) as an input signal. In this paper Adaptive Noise Cancellers are implemented by utilizing gradient based algorithms, swarm-based algorithm and nature inspired algorithm which is Grey Wolf Optimization (GWO). To improve the ANC performance, an optimal weight value is calculated and GWO is used to update optimal weight value. Testing of an adaptive filter has been done through consideration of White Gaussian Noise (WGN) over sample input EEG signals at various SNR levels. The performance of the GWO algorithm is evaluated in terms of mean value, Signal to Noise Ratio (SNR) in dB and correlation. A comparative analysis shows that proposed GWO technique gives better performance when compared with the gradient-based techniques like RLS, LMS and swarm-based technique like Particle Swarm Optimization (PSO). The novelty of this proposed approach can be considered, as because first-time GWO is applied on denoising EEG signals from the contaminated EEG signal, the result shows that extracting the desired EEG component is more effective in the proposed GWO method.

Modern communication systems rely on Digital Signal Processing (DSP) more than ever before. Improving the speed of FFT computation using high speed multipliers will help to enhance the performance of DSP systems. In this paper a DIT FFT architecture using high performance Modified Vedic multipliers is proposed. Vedic Multipliers offer a more efficient way to perform multiplication on large numbers occupying less area and consuming low power and delay The adders used in the Vedic multipliers are Brent Kung based and multiplexer based adders. The right utilization of these adders at different word lengths helps to achieve an architecture with minimal area and power. Comparative analysis of modified 24×24 Vedic Multiplier with existing Vedic Multiplier shows the improvement in performance with respect to power and area. Proposed FFT design is compared with existing designs for dynamic power consumption and an improvement of 46.93% compared to Tsai’s FFT Design and 59.37% compared to Coelho’s FFT Design is achieved. The entire architecture is implemented on Virtex 7 FPGA and simulated using Xilinx Vivado 2017.4.

World has become digital nowadays and networking is a key feature of this changing globe. Key information of official transactions to social life of an individual, all lie on a network which has attracted researchers towards network security as an important issue to deal with. A number of encryption and decryption techniques have developed since years, Advanced Encryption Standard (AES) being the most popular and highly efficient. This paper proposes an extended implementation of 128 bit AES block along with four blocks of 32 bit Arithmetic and logic units (ALU). The extended set ALU with Manchester encoder decoder, Parity Generator, Parity checker, Binary to gray and Gray to Binary convertor is used for enhanced security. The proposed model provides flexibility at user level to switch between various security options. Complete design is implemented on 28nm zynq 7000 FPGA board using Xilinx Vivado tool.

Two new configurations to realize high input impedance biquadratic filter functions employing three translinear current conveyors (CCCII) few capacitors and resistors are presented in this paper. First configuration is capable of realizing band pass filter while second can realize all-pass and notch filter function. The above filters have better input impedance, we can say good for cascading to implement the other higher order filters. The grounded passive components like capacitors make it attractive for integration. The circuit also gives best matching conditions for active and passive sensitivities. The simulated results are very well matched with theoretical analysis.

This paper presents a new dual V t 8 T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation(WARI). Also a faster write back scheme is proposed for the half selected cells. A high V t device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin(RSNM) due to the bit-line isolation during the read. Static noise margins for data read(RSNM), write(WSNM), read delay, write delay, data retention voltage(DRV), leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8 T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.

This paper discusses the implementation of variants of LMS (Least Mean Square) algorithm on new model named as Suspended Feedback (SuFee). Implementation of LMS (Least Mean Square) algorithm along with its variants like Constraint Stability Least Mean Square (CSLMS) and Non-Linear Data Least Mean Square (NDLMS) with conventional model and new SuFee model has been done. This model is an advanced version of conventional adaptive noise canceller. It is a simulation-based signal flow model. The conventional and SuFee models are evaluated and simulated using MATLAB, taking speech as an input signal mixed with white noise. The new SuFee model provides an advantage of faster error convergence with significant improvement in the output quality of the signal. Convergence was evaluated by displaying the learning curves and error signals of the different adaptive filter algorithms. Signal to Noise Ratio(SER) is the parameter to evaluate the quality of the output signal. The result shows the signal quality has been enhanced by three times better than the conventional model.

High Electron Mobility Transistor (HEMT) based on GaN are being widely used in defense for wireless communication, in radar for airborne strategic applications. GaN material properties like mobility, self-heating, band gap and 2DEG concentration are very crucial for optimum device performance and needs to be optimized. AlGaN/GaN HEMTs have become superb device in power electronics as well as for application in high frequency range because of their high 2-D electron gas density along with their high breakdown electric field and electron mobility. HEMTs device gate length influences the cutoff frequency, transconductance and maximum frequency of oscillation. Research is going on to improve the high-frequency characteristics by reducing the gate length. The effect of self-heating of the device on gate length is an important parameter which has been rarely investigated.

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line(BNBL) provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line(NBL) and boosted bit line(BBL) write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.

InAs schottky barrier gate all around MOSFET has been studied. Its electrical characteristics has been studied by simulating the device in a multiphysics simulation software. A 2D device was simulated, because of the symmetry of a cylinder and later extruded into a 3D structure to get appropriate results. The device parameters such as band diagram, current characteristics and small signal parameters such as drain conductance and transconductance have been studied by varying the drain and gate voltages.