A long-term temperature cycle test has been running for more than 13 years to answer the most challenging questions about dominating failure modes and degradation processes caused by thermal cycle loadings close to service conditions. Test boards with components QFN40, QFN36,FBGA48, TQFP100, FBGA227 and chip capacitors/resistors size 0201 have been subjected to temperature cycles 18°C/80°C, 7.1 hours. The latter three were analyzed by Finite Element Analysis (FEA) and compared to damage observed from cross sectioning up to damage states at approx. 15.700 cycles (13 years). SAC357 (Sn3.5Ag0.7Cu) was used. Solder fatigue was clearly the dominating failure mechanism for all components except the 0201 ceramic chip capacitors/resistors.SAC solder fatigue is briefly discussed from a microstructural and continuum mechanical perspective. Fatigue life evaluation results based on averaged cyclic creep strain and creep dissipation are compared to testing results. The fatigue life prediction model based on the secondary/primary creep law tends to predict fatigue life reasonably well for test cycling but underestimates it for field cycling. Simulation inherent issues like the use of a combined secondary/primary creep model vs. two Anand’s models from the literature are also addressed.Some failure modes apart from standard ductile solder fatigue are discussed for thermal test-and field-conditions.

The use of electronics for purpose of autonomous driving requires high performance vehicle computer (HPVC) systems usable in harsh environments. A variety of challenging issues have to be considered from different perspectives. The paper focuses on the perspective of reliability and functional safety. To physically simulate and to analyze the thermal and the thermo-mechanical behaviors of the actual processors in different operation modes, a mock-up system is designed, which has initially been modelled by virtual means. The thermo-mechanical design methodology is essentially based on FE parametric studies, using a full model including 1st and 2nd level interconnects as well as including solder creep and other materials non-linearity.. To gain an overview on overall influences of materials parameters choice, virtual DOE was made at the beginning. Model complexity and size limits virtual DOE, which was performed with reduced geometric details and elastic material modeling. Comparison on material models comprise visco-plastic models for SAC305 and visco-elastic models for polymers. To reach high T-cycle reliability is a challenge for the mock-up system. The effects were analyzed for both first level and second level interconnects. It is shown that first level bumps fatigue or underfill 1 delamination are highest failure risks, which can be basically affected by choice of the assembly technology, i.e. underfill/undermold and soldermask choices. Simulation inherent issued like the use of a combined secondary/primary creep model vs. an Anand's model are compared and good agreement has been observed.