This article presents a two-stage approach for the processing of frequency-stacked mobile subbands. The frequency stacking is performed in the analog domain to enable the use of a wideband analog-to-digital converter (ADC), instead of employing multiple narrowband ADCs, to support multiple antenna elements for digital satellite beamforming. This analog front end provides a common broadband digital interface to the on-board processor and can be configured to support multiple satellite missions, reducing the cost of commissioning a digital processor for individual satellite missions. This article proposes a framework on the specification of digital prototype filter for the analysis of frequency-stacked mobile subbands. The computational complexity of the analysis operation, with two digital filter alternatives, are evaluated. A series of results, taken from our European Space Agency sponsored project, are presented here to demonstrate the applicability of the proposed two stage approach, reporting on the savings in power consumption when an Nth-band all-pass-based recursive filter having an infinite impulse response is used as the digital prototype filter.

Frequency stacking in the analog domain is used to replace multiple narrowband ADCs with a wideband ADC, supporting multiple antenna elements for digital satellite beamforming. This analog front end provides a cost-effective solution by offering a common broadband digital interface to the onboard processor, which can be configured for multiple satellite missions. This paper is on specifying the prototype filters to analyse frequency-stacked mobile sub-bands in the digital domain. The paper further presents results and observations that demonstrates the effectiveness of this specification for a given mobile narrowband communication scenario. Index Terms—Satellite Communication Systems, Digital Signal Processing, Analog-to-Digital Convertor.

Today, the increasing demand in higher data rates necessitates new methods as well as higher flexibility for satellite telecommunication payloads in order to address a variety of applications and customers. This paper presents one of these processing strategies that is applicable to today's processing satellite payloads aiming to meet those demands. For this purpose, a two-tier filter bank is designed as part of a digital on-board processor, which first divides the spectrum at the output of the ADC into a number of sub-bands extracting all the stacked channels in the digital domain. Following the analysis section of the first tier of operations, the extracted channels go under a secondary channelisation process to obtain much finer granularity of 31.25 kHz or 50 kHz depending on the communication standard used for data transmission. The implementation of the channeliser was delivered on a bit-true simulation model and the input and the output of the channelisers were compared and evaluated both in the time and frequency domains.

In this paper a novel pipelining approach applicable to Winograd Fourier transforms is presented. The novel approach makes use of reconfigurable multiplier blocks to implement the real multipliers required for the transform as well as sharing the hardware resources among additions. The additions are realized using modified forms of butterfly circuits. The novel approach is tested on a 5-point Winograd Fourier transform and the circuit area and power dissipation of the design are estimated using an in-house power estimation tool and compared to the state-of-the-rt approaches.

Fast Fourier Transform (FFT) and Discrete Fourier Transform (DFT) are the two very important building blocks of an On-Board Processor (OBP). Not only to enable processing in the frequency domain but also to perform demultiplexing/multiplexing tasks, transforms like the FFT and the DFT are widely in use. In this paper we will look at parallelisation of the FFT/DFT structures, which necessitates the decomposition of these transforms. The decomposition of the FFT or DFT into two or more smaller transforms may bring in extra operations in the form of twiddle multiplications. In this paper we will introduce an efficient strategy to store twiddle factors for the decomposed FFT/DFT processing blocks, where both the memory size and the number of accesses to the memory are minimized in comparison to the conventional methods. We designed a clever address generator unit and made use of a reduced memory approach and set the content of the memory accordingly, where the strategy is to decrease both the circuit area and the power dissipation in the FFT/DFT block to be used on the satellite's digital processing payload.

A high-throughput processor concept is being developed under the auspices of an ESA contract. It relates to a high-capacity, broadband satellite system for access networks that provides regional (e.g. European) coverage through a large number (>100) of broad-band user beams. At the heart of the system lies a transparent digital signal processor, which provides the necessary flexibility in beam routing and frequency mapping. Transparent digital signal processors are an established pedigree in mobile systems like Inmarsat 4. However, the capacity of High-Throughput-approximately 50 GHz-is vastly larger than in previous systems; thus High-Throughput represents a significant step forwards in transparent processor architecture and technology. This paper presents the details of an FPGA-based demonstrator of the High-Throughput processor, which is a scaled-down version of the full system design. The demonstrator implements complete (de)multiplexing, switching and beam-forming algorithms, all of which process at the full system rate (500 MHz per port). Accompanying the demonstrator processor is a flexible broad-band signal generation and analysis module, which provides means of generating stimulus and measuring the processorpsilas performance.

In order to compete with terrestrial services, satellite systems for broadband access networks must maximise the useful capacity provided by each satellite. The High Throughput system has been carefully optimised in terms of capacity as part of an ESA R&D contract. This system provides Kaband links between approximately one hundred user beams and a network of gateway stations over a regional European coverage from geostationary orbit. On-board digital processing is essential in providing the routing and frequency plan flexibility needed to use the resources efficiently across so many spot beams. Despite the large bandwidths involved, recent advances in ASIC, mixed signal conversion and digital interconnect technologies, make a fully processed payload handling up to 50 GHz of processed bandwidth feasible in the relatively near term. As well as fine channel demultiplexing, fully flexible routing and gain control, the digital processor also supports digital beamforming across a 500 MHz band, allowing for flexible frequency reuse and coverage that can be reconfigured in orbit. All these functions can be demonstrated at speed for a reduced number of processing chains using currently available commercial off-the-shelf FPGA-based processing cards.