This paper outlines the Nallatech Accelerator Layer (NAL) and its relationship to Intel’s Accelerator Abstraction Layer. The NAL is looked at in its academicion Layer. The NAL is looked at in its academic context. Hardware platforms that support the NAL are discussed: the Nallatech H101, the Intel FSB-FPGA Module and the BenOne PCIe. The Intel QuickAssist Technology initiative and its associated Accelerator Abstraction Layer (AAL) are introduced.ion Layer (AAL) are introduced. To demonstrate the NAL system, two closed-form expressions are implemented. These functions are singleprecision floating-point, and make use of arithmetic operations and elementary functions. The functions selected were the probability density function (PDF) and the Black-Scholes-Merton options pricing formula (BSM). These functions were implemented on a dual-core Opteron, a Nallatech H101 card using the NAL, a Nallatech BenOne PCIe card, an NVIDIA G80 using CUDA and a Cell BE system. The GPU system showed the best silicon performance for the implementation of these kernels. Including data transfer times, the BenOne PCIe had the highest performance.

FPGAs have established performance advantages over other processing technologies. Difficulties in achieving high design productivity counterbalance these performance advantages. High-level languages (HLLs) targeting FPGAs together with low-level core libraries have the potential to overcome these productivity challenges. It is desirable to possess an industry standard for the integration of core libraries into FPGA HLLs. The OpenFPGA CORELIB group is working towards this end. The authors present an implementation of a core library: A library of floating-point elementary transcendental functions targeted at DIME-C, an FPGA HLL, and Xilinx Virtex-4 FPGAs. The paper contrasts three methods of creating pipelined mathematical cores: Using DIME-C creation, using VHDL and using System Generator. Implementation results, comparisons with software and general conclusions about elementary functions on FPGAs are given.

Since their invention in the 1980s, the logic density of FPGAs has increased exponentially with time. This increase of logic density first led to the development of synthesisable HDLs, and is now leading to the development of high-level languages that target FPGAs (FPGA HLLs). There is now a range of C-to-VHDL compilers, FPGA HLLs that use variant of the ANSI C syntax as their input. These languages have many features in common, as well as distinguishing features. The authors present Nallatech's DIME-C compiler, its features and its novelties. The DIME-C compiler has been used to program a 64-node FPGA supercomputer created as part of the FPHCA project [7]. Using DIME-C to program the supercomputer resulted in significant performance increases (up to 11 Ox) and increased productivity. Some conclusions on design methodology are then drawn.

Research into the use of FPGAs in Image Processing began in earnest at the beginning of the 1990s. Since then, many thousands of publications have pointed to the computational capabilities of FPGAs. During this time, FPGAs have seen the application space to which they are applicable grow in tandem with their logic densities. When investigating a particular application, researchers compare FPGAs with alternative technologies such as Digital Signal Processors (DSPs), Application-Specific Integrated Cir-cuits (ASICs), microprocessors and vector processors. The metrics for comparison depend on the needs of the application, and include such measurements as: raw performance, power consumption, unit cost, board footprint, non-recurring engineering cost, design time and design cost. The key metrics for a par-ticular application may also include ratios of these metrics, e.g. power/performance, or performance/unit cost. The work detailed in this paper compares a 90nm-process commodity microprocessor with a plat-form based around a 90nm-process FPGA, focussing on design time and raw performance. The application chosen for implementation was a minimum entropy restoration of star-field images (see [1] for an introduction), with simulated annealing used to converge towards the globally-optimum solution. This application was not chosen in the belief that it would particularly suit one technology over another, but was instead selected as being representative of a computationally intense image-processing application.

This presentation details the initial stages of a project whose aim is to provide developers with an FPGA-implemented implementation of the VSIPL API.