The performance and reliability of submicron CMOS circuits have been affected by hot-carrier stress induced degradation. Three common forms of CMOS latch circuits designed using a 0.7-micron commercial process have been considered in a comparative study of the stress levels experienced by individual devices in the circuit. Average stress levels on all the devices over a typical simulation cycle was used to assess the life-time and the reliability of the circuits. We describe a technique that was used to identify the devices having higher than normal stress which may consequently degrade at a faster rate than other devices leading to an early failure of the circuit. We have developed design techniques that can be used to reduce the stress levels in identified devices. The improvements in life-time and reliability have been assessed and analysed. The best circuit configuration to reduce hot-carrier stress induced degradation has been identified. (C) 1998 Elsevier Science Ltd. All rights reserved.

The authors describe a mechanism which allows CMOS circuits containing a break in a power supply track (referred to as open circuit supply faults) to operate with little change in their performance parameters. In circuits containing such faults, current can be supplied through the substrate or well contacts enabling logic gates to operate at full design speed. Measurements on circuits containing such faults and results of simulations are presented to demonstrate the effect of the fault. The circuits operate normally, although they may be susceptible to latch-up behaviour and may fail in this way. Transient latch-up testing is recommended to detect such faults