Growing on-chip wire delays, coupled with complexity and power limitations, have placed severe constraints on the issue-width scaling of centralized superscalar architectures. As a result, recent microprocessor designs have backed away from powerful uniprocessors, instead favoring multiple simpler cores on a single die. Partitioning the chip into a collection of processors communicating via a common memory system mitigates some of the technology scaling challenges, but increases the burden on software to provide multiple threads to execute concurrently across the cores. An alternative is to pursue more powerful uniprocessors, but design them so that they are scalable and tolerant of technology and complexity scaling. Ideally, such wide-issue processors would be tiled [30], meaning composed of multiple replicated, communicating design blocks. Because of multicycle communication delays across these …

The TRIPS hardware prototype is the first instantiation of anExplicit Data Graph Execution (EDGE) architecture. Building the com piler, toolset, and system software for the prototype required sup porting the system's unique dataflow construction, its banked registerand memory configurations, and its novel Instruction Set Architecture . In particu- lar, the TRIPS ISA includes (i) a block atomic execution mode l, (ii) ex- plicit mappings of instructions to execution units, and (ii i) predicated instructions which may or may not fire, depending on the outco me of preceding instructions. Our primary goal has been to cons truct tools to consume standard C and Fortran source code and gener ate binaries both for the TRIPS software simulators and hardwar e proto- type. A secondary goal has been to build the software infrast ructure on standard platforms using standard tools. These goals have b een met through a combination of off-the-shelf and custom tools. Wepresent a number of design issues and their resolution in enabling en d users to exercise the prototype ISA using familiar tools and progr amming interfaces. Finally, we offer download instructions for th ose who wish to test-drive the TRIPS tools.

Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB non-uniform (NUCA) on-chip memory system

The TRIPS hardware prototype is the first instantiation of an Explicit Data Graph Execution (EDGE) architecture. Building the compiler, toolset, and system software for the prototype required supporting the system’s unique dataflow construction, its banked register and memory configurations, and its novel Instruction Set Architecture. In particular, the TRIPS ISA includes (i) a block atomic execution model, (ii) explicit mappings of instructions to execution units, and (iii) predicated instructions which may or may not fire, depending on the outcome of preceding instructions. Our primary goal has been to construct tools to consume standard C and Fortran source code and generate binaries both for the TRIPS software simulators and hardware prototype. A secondary goal has been to build the software infrastructure on standard platforms using standard tools. These goals have been met through a combination of off-the-shelf and custom tools. We present a number of design issues and their resolution in enabling end users to exercise the prototype ISA using familiar tools and programming interfaces. Finally, we offer download instructions for those who wish to test-drive the TRIPS tools.