In recent years, there has been a large push in the U.S. Department of Defense (DoD) to more rapidly respond and adapt to changing technology advancements and emerging communications systems threats. One issue has been that traditional DoD waveform development has been stove-piped in that processing blocks are implemented to serve a single function instead of made generic and configurable to support multiple waveforms. Developing new waveforms typically requires starting from scratch almost everytime. In this paper, we present Common Hardware-modem Integrated Library (CHIL). CHIL is both a library of configurable processing blocks as well as a framework that ties these blocks together to rapidly instantiate new DoD and non-DoD waveforms. We present an overview of the CHIL framework and various components as well as provide a test-case where CHIL was leveraged to instantiate a DoD waveform.

Emulation of tactical wireless networks in a laboratory environment provides a cost-effective solution for development tests and serves as a risk reduction for formal operational tests. However, laboratory-based emulation of tactical Mobile Ad Hoc Networks (MANETs) is particularly challenging due to the complex nature of the underlying environment. Unlike point to-point systems, emulation of MANETs requires the execution of multiple channels in parallel. Furthermore, tactical wireless channels are susceptible to impairments such as fading, Doppler, multipath, and jamming, which further complicates the ability to replicate such environments in a controlled laboratory setting. In this paper, we evaluate a previously developed Digital Wireless Channel Emulator (DWCE) by comparing field test results with data collected in an emulated environment for a 29 node tactical MANET. We present our approach for obtaining relevant metrics from the field and describe our methodology for comparison from both a qualitative and quantitative perspective.

A Radio Frequency (RF) Wireless Channel Emulator (WCE) is technology used to emulate the RF environment for wireless devices so they can be evaluated in a laboratory while reproducing channel effects otherwise seen in the field. This increases the repeatability of evaluations, saves time and money in logistical and programmatic costs, and can analyze real world situations, such as an actual battlefield prior to engagement or the effect of a radio mounted on an aircraft. The types of scenarios are endless. All this benefit is relatively meaningless however, if the evaluator does not have confidence that the WCE will produce the same effects that would be seen in the real world. This paper is a validation study of a specific WCE, the Digital Battle space Environment Simulator (DBES) and provides a framework by which other channel emulators could be compared. A methodology for evaluating the fidelity of a channel emulator by measuring several key components is described. These components are analyzed experimentally and compared against the theoretical ideal without being radio specific. After this analysis had been completed several scenarios were run with radios in order to observe the results.

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of wireless devices. A major issue with current designs is that they do not scale to a large enough number of nodes to emulate meaningful network. A reason for this lack of scalability is the large amount of computations and network capacity required for such a system. Previously documented DWCE systems implement a hub-and-spoke configuration that inhibits them from simply adding additional hardware to scale. This paper investigates the use of a FPGA cluster configured as a distributed system to provide the computational and network structure to scale a DWCE to support 1250 wireless devices. This scale is approximately two orders of magnitude larger than any other previously documented system. This paper presents multiple FPGA cluster configurations that use currently available hardware and describes the algorithms used to route the signals through the network and place the computational hardware on each FPGA. The low level VHDL Signal Path Component(SPC) is synthesized and mapped under different parameters to interpolate is resource utilization. One example FPGA build with enough SPCs to fill 80% of the FPGA resources is successfully run through the Xilinx tool-chain to determine the maximum FPGA system clock speed. Finally, the scaling results are presented that detail the maximum sample frequency of various sized DWCE systems which could be used to examine a variety of wireless devices.

The Reconfigurable Computing Cluster project has been investigating broad question of what, if any, role FPGAs may play in parallel computing. While this article does not answer that question but describes the experiences thus far. The main vehicle for research has been Spirit, a small-scale experimental machine consisting of 64 FPGAs connected in 3-D torus. It has been at the core of several focused studies. This article provides a summary of the architecture, the scientific and pragmatic discoveries enabled by the machine, and two more FPGA-based parallel computers that are presently under development.

A Digital Wireless Channel Emulator (DWCE) is a system that is capable of emulating the RF environment for a group of radios. A major issue with current designs is that they do not scale to a large enough number of nodes to emulate meaningful network due to the amount of computations required for such a system. This paper proposes a novel DWCE design based on a cluster of FPGA devices. By decentralizing the signal processing it is possible to increase the available computational resources to the point where they are no longer the limiting factor to scalability. It demonstrates feasibility by analyzing the computational and network requirements of the application and showing how the proposed design meets those needs. The paper also describes the physical design of a new 64 node FPGA cluster that is being manufactured. An implementation on prototype nodes of this cluster demonstrates the machine will support a high fidelity emulation for 32 radios or a lower-fidelity emulation for 128 radios.

The utilization of digital Wireless Channel Emulators (WCE) with networking radios is hampered by the inability to efficiently scale a digital WCE to a large number of nodes. While analog WCEs are capable of large numbers of nodes they cannot cost effectively emulate channel effects such as fading and multipath which significantly limits the accuracy and flexibility of the emulation. If such a large scale digital WCE were to exist, a significant amount of time and money could be saved by testing networking radios in a laboratory before running lengthily and costly field tests. By utilizing the repeatability of a laboratory environment it will be possible to investigate and solve issues more quickly and efficiently. This will enable the performance of the radios to be known with a high degree of certainty before they are brought to the field. This paper describes research into scalability of digital wireless channel emulators highlighting technical challenges and presents a design solution that will meet the needs of current and future networking radio system testing. The major design challenges of the system include: computational and network capability, end-to-end propagation delay, and accuracy of the emulation. A solution to these issues involves the creation of an FPGA computational cluster networked via high speed transceivers and a signal path design that utilizes hardware resources effectively. A prototype was developed using this signal path design and COTS hardware to explore each of the challenges and to take metrics demonstrating the capability of a full scale system to meet these challenges. Additionally, this prototype was connected to Joint Tactical Radio Systems (JTRS) radios to demonstrate the capabilities of the system with military hardware.

The Reconfigurable Computing Cluster project has been investigating broad question of what, if any, role FPGAs may play in parallel computing. While this article does not answer that question but describes the experiences thus far. The main vehicle for research has been Spirit, a small-scale experimental machine consisting of 64 FPGAs connected in 3-D torus. It has been at the core of several focused studies. This article provides a summary of the architecture, the scientific and pragmatic discoveries enabled by the machine, and two more FPGA-based parallel computers that are presently under development.