The Water Cherenkov Detector Array (WCDA) is one of the major components of the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered over a 90000 m2 area, while high precision time measurements (0.5 ns RMS) are required in the readout electronics. To meet this requirement, the clock has to be distributed to the FEEs with high precision. Due to the "triggerless" architecture, high speed data transfer is required based on the TCP/IP protocol. To simplify the readout electronics architecture and be consistent with the whole LHAASO readout electronics, the White Rabbit (WR) switches are used to transfer clock, data, and commands via a single fiber of about 400 meters. In this paper, a prototype of data and clock transmission interface for LHAASO WCDA is developed. The performance tests are conducted and the results indicate that the clock synchronization precision of the data and clock transmission is better than 50 ps. The data transmission throughput can reach 400 Mbps for one FEE board and 180 Mbps for 4 FEE boards sharing one up link port in WR switch, which is better than the requirement of the LHAASO WCDA.

In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the major detectors. The WCDA electronics are responsible for the readout of 3600 Photomultiplier Tubes (PMTs), and a total of 400 Front End Electronics (FEE) modules are required. The main challenges in the WCDA readout electronics design include: precise time and charge measurement over a large dynamic input amplitude range (1 Photo Electron (P.E.) ~ 4000 P.E.), high quality of clock distribution and automatic clock phase compensation, and high speed data transfer due to the requirement of “triggerless” architecture. In this paper, we present the prototype design of the readout electronics for the LHAASO WCDA. We also conducted tests on the prototype electronics to evaluate the performance. The results indicate that a charge resolution better than 15%@ 1 P.E. and 2%@ 4000 P.E., and a time resolution better than 0.3 ns RMS are successfully achieved over the whole dynamic range, beyond the application requirement.

The Water Cherenkov Detector Array (WCDA) is one of the key parts of the Large High Altitude Air Shower Observatory (LHAASO). In WCDA, the high precision time and charge measurement are required for 3600 Photomultiplier Tubes (PMTs) scattered over a 90000 m 2 area. With a distributed architecture, the 400 Front End Electronics (FEEs) placed near the PMTs are responsible for the time and charge measurement over a large dynamic range. The time measurement resolution is required to be better than 0.5 ns RMS and the required resolution for the charge measurement is better than 30% @ 1 Photo Electron (P.E.) and 3% @ 4000 P.E. Considering the large scale of the detector area, high precision clock distribution and automatic phase compensation over long distances is required. To simplify the electronics structure, clock, data and commands are transmitted together over the same optical fiber media. To evaluate the prototype FEE performance, we conducted a series of tests, including performance tests both with constant and changing ambient temperature. Test results indicate that time and charge measurement resolution and clock synchronization satisfy the application requirement.

In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO), both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. for the PMT signal readout. In this paper, we present our work on the design of time discrimination circuits in LHAASO WCDA, especially on improvement to reduce the circuit dead time. Several approaches were studied through analysis and simulations, and actual circuits were designed and tested in the laboratory to evaluate the performance. Test results indicate that a time resolution better than 500 ps RMS is achieved in the whole large dynamic range, and the circuit dead time is successfully reduced to less than 200 ns.

The Water Cherenkov Detector Array (WCDA) is one of the key parts in the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered within a 90000 m(2) area, while a time measurement resolution better than 0.5 ns is required in the readout electronics. To achieve such time measurement precision, high quality clock distribution and synchronization among the 400 FEEs (each FEE for 9 PMTs readout) is required. To simplify the electronics system architecture, data, commands, and clock are transmitted simultaneously through fibers over a 400-m distance between FEEs and the Clock and Data Transfer Modules (CDTMs). In this article, we propose a new method based on the White Rabbit (WR) to achieve completely automatic clock phase alignment between different FEEs. The original WR is enhanced to overcome the clock delay fluctuations due to ambient temperature variations. This paper presents the general scheme, the design of prototype electronics, and initial test results. These indicate that a clock synchronization precision better than 50 ps is achieved over 1 km fibers, which is well beyond the application requirement.

The invention discloses a high-precision clock distribution and phase automatic compensation system and a phase adjusting method thereof. The system comprises a clock distribution module (master) and a plurality of front-end electronics nodes (slave). The master distributes clocks to the multiple slaves by using fibers. The master sends the clocks to the slaves by the fibers; after receiving the clocks, the slaves return the clocks to the master again; the master carries out dynamic measurement on the sum of round-trip time of the clocks to obtain uplink and downlink delay time of the clocks and sends measurement results to the slaves; and according to the measurement results, the slaves carries out dynamic phase adjustment on the received clocks, so that phase synchronization of the slaves and the master can be maintained. With the system and method, the phase synchronization precision is improved and a phase adjustment error caused by the temperature change can be reduced.

The time-to-digital converter(TDC) is an equipment which aims to measure the accurate time of the edges of the input signal. Our work present an I/O Tile based multi-phase clock time-to-digital TDC, which is implemented in Field-Programmable-Gate-Array(FPGA). A hit signal is sampled by 8 equidistant phase-shifted clocks in the I/O Tile. A differential I/O standard input signal connecting to the I/O Tile is buffered by an input buffer and split into two complementary outputs before feeding to two adjacent ISERDESes. The ISERDESes are configured as the oversample mode, which is used to capture 2 phase DDR data. One ISERDES is driven by 45° and 135° clocks, with the other ISERDES driven by 90° and 180° clocks. Four more clocks are produced by locally inverting logic in the two ISERDESes. An internal PLL is used to generate the clocks. This architecture makes the transmission line more stable and increases the frequency of the sampling clock. To evaluate the TDC's performance, we built a verification system with Xilinx Artix-7 XC7A100T-1 FPGA, which is integrated with 2 TDCs and a readout unit. Tests have been conducted on the performance of the I/O Tile based TDC. Results indicated that the integral nonlinearity is lower than 1 LSB, and the differential nonlinearity is lower than 0.32 LSB. The measurement resolution of 56ps (RMS) is archived.

The data transfer interface of the Front End Electronics ( FEE) is designed in for the Water Cherenk-ov Detector Array ( WCDA) in Large High Altitude Air Shower Observatory ( LHAASO) .To meet the require-ment of high-speed data transfer over many front end nodes scattered in a large area, a data transfer interface is specially designed based on the TCP/IP protocol and 1000 M ethernet, which is implemented using the em-bedded system in an FPGA device.Test results in the laboratory indicate that a data transfer rate more than 237 Mbps is achieved, beyond the application requirement.We also conducted 24-hour tests to evaluate the stabil-ity of the data transfer speed, also with good results as expected.

The time-to-digital converter(TDC) aims to mark an accurate timestamp at the time of input signal comes. The Multi-phase Clock sampling method is an usual way to map the TDC into an FPGA. Traditionally, this method provides a medium accuracy and low resources occupation. In this paper, we present a new architecture of TDC base on the 2-ISERDES in the SelectIO, rather than utilizing the Slice resources by the old way. The ISERDESes based TDC is equivalent to a 8 equidistant phase-shifted clocks TDC, with maximum clock frequency 900MHz. The least significant bit(LSB) is 139ps, which is 445% better than traditional architecture.