This paper presents Simultaneous Speculative Threading (SST), which is a technique for creating high-performance area- and power-efficient cores for chip multiprocessors. SST hardware dynamically extracts two threads of execution from a single sequential program (one consisting of a load miss and its dependents, and the other consisting of the instructions that are independent of the load miss) and executes them in parallel. SST uses an efficient checkpointing mechanism to eliminate the need for complex and power-inefficient structures such as register renaming logic, reorder buffers memory disambiguation buffers, and large issue windows Simulations of certain SST implementations show 18% better per-thread performance on commercial benchmarks than larger and higher-powered out-of-order cores. Sun Microsystems' ROCK processor, which is the first processor to use SST cores, has been implemented and is scheduled to be commercially available in 2009.

Rock, Sun's third-generation chip-multithreading processor, contains 16 high-performance cores, each of which can support two software threads. Rock uses a novel checkpoint-based architecture to support automatic hardware scouting under a load miss, speculative out-of-order retirement of instructions, and aggressive dynamic hardware parallelization of a sequential instruction stream. It is also the first processor to support transactional memory in hardware.

......Designing an aggressive chipmultithreaded (CMT) processor involves many tradeoffs. To maximize throughput performance, each processor core must be highly area and power efficient, so that many cores can coexist on a single die. Similarly, if the processor is to perform well on a wide spectrum of applications, per-thread performance must be high so that serial code also executes efficiently, minimizing performance problems related to Amdahl’s law. Rock, Sun’s third-generation chip-multithreading processor, uses a novel resource-sharing hierarchical structure tuned to maximize performance per area and power. Rock uses an innovative checkpoint-based architecture to implement highly aggressive speculation techniques. Each core has support for two threads, each with one checkpoint. The hardware support for threads can be used two different ways: a single core can run two application threads, giving each thread hardware support for execute ahead (EA) under cache misses; or all of a core’s resources can adaptively be combined to run one application thread with even more aggressive simultaneous speculative threading (SST), which uses two checkpoints. EA is an area-efficient way of creating a large virtual issue window without the large associative structures. SST dynamically extracts parallelism, letting execution proceed in parallel at two different points in the program. These schemes let Rock maximize throughput when the parallelism is available, and focus the hardware resources to boost per-thread performance when it is at a premium. Because these speculation techniques make Rock less sensitive to cache misses, we have been able to reduce on-chip cache sizes and instead add more cores to further increase performance. The high core-tocache ratio requires high off-chip bandwidth. Rock-based systems use large caches in the off-chip memory controllers to maintain a relatively low access rate to DRAM; this maximizes performance and optimizes total system power. To help the programmability of multiprocessor systems with hundreds of threads and to improve synchronization-related performance, Rock supports transactional Shailender Chaudhry Robert Cypher Magnus Ekman Martin Karlsson Anders Landin Sherman Yip Håkan Zeffer Marc Tremblay