The bootloader is a critical part of a device’s secure startup, and its interactions with firmware images require cryptographic operations. Instead of storing keys for authentication and encryption in the bootloader, one can harden the system by offloading the key storage and all cryptographic operations to a secure element. This paper analyzes the susceptibility of MCUboot used in conjunction with a secure element to voltage fault injection during firmware image verification. We designed and built a low-cost voltage fault injection tool using a Cortex-M7 MCU and an analog switch, which can achieve a timing resolution of 6.67 ns. We found vulnerable instructions in the glue code between the bootloader and the secure element library. By targeting these vulnerable instructions, we showed how an attacker could bypass a signature verification performed by a secure element by faulting a Nordic nRF52840 host MCU. While secure elements are still suited for securely storing keys and other sensitive data, a holistic approach is required to secure a device against fault injection. Otherwise, the threat of fault injection could diminish the benefits of secure bootloaders and secure elements.

Safety-critical wireless sensor networks, such as a distributed fire- or burglar-alarm system, require that all sensor nodes are up and functional. If an event is triggered on a node, this information must be forwarded immediately to the sink, without setting up a route on demand or having to find an alternate route in case of a node or link failure. Therefore, failures of nodes must be known at all times and in case of a detected failure, an immediate notification must be sent to the network operator. There is usually a bounded time limit, e.g., five minutes, for the system to report network or node failure. This paper presents DiMo, a distributed and scalable solution for monitoring the nodes and the topology, along with a redundant topology for increased robustness. Compared to existing solutions, which traditionally assume a continuous data-flow from all nodes in the network, DiMo observes the nodes and the topology locally. DiMo only reports to the sink if a node is potentially failed, which greatly reduces the message overhead and energy consumption. DiMo timely reports failed nodes and % greatly minimizes the false-positive rate and energy consumption compared with other prominent solutions for node monitoring.

Compositional approaches to system-level performance analysis have shown great flexibility and scalability in the design of heterogeneous systems. These approaches often assume certain system architectures and application domains, and are thus tailored to give tight analysis results for specific systems. We consider two different compositional analysis methods. Both methods have their particular strengths for different architectures and applications. In this paper, we aim to enhance the analysis capabilities for these techniques. A method for event model conversion allows us a seamless integration of the two methods. Finally, we present a detailed case study to show the applicability and benefits of the enhanced performance analysis technique.

Recent research on performance analysis for embedded systems shows a trend to formal compositional models and methods. These compositional methods can be used to determine the performance of embedded systems by composing formal analytical models of the individual components. In case there exist no formal component models with the required precision, simulation-based approaches are used for system-level performance analysis. The often high runtimes of simulation runs lead to the new approach described in this paper: Analytical methods are combined with simulation-based approaches to speed up simulation. We describe how the simulation models can be coupled with the formal analysis framework, specify the interfaces needed for such a combination and show the applicability of the approach using a case study

System-level performance-evaluation methods for computer and communication systems can be divided into two main areas: simulation and analytic methods. Analytic methods are often fast but rather coarse, whereas simulation is time-consuming but often leads to more accurate results. Therefore, there is the need to (a) determine analytic models from simulation results, actual measurements or formal specifications and (b) to generate representative event traces from analytic models. Whereas there are many results available in case of statistical analytic models, there are no methods known for other forms of variability characterizations. The method presented in this paper is suited for arrival curves, a widely accepted tool for traffic characterization. In addition, this class of event models has been successfully used to perform a modular performance, end-to-end delay and buffer size analysis of distributed computer and communication systems. In particular, we propose a new method to generate event traces for simulation or physical measurements, starting from a formal specification of event streams in form of arrival curves. In addition, a quality indicator is defined to evaluate the generated traces. Finally, experiments are described that show the applicability of the approach.

In this paper we propose several efficient algorithms for assessing the resistance of Boolean functions against algebraic and fast algebraic attacks when implemented in LFSR-based stream ciphers. An algorithm is described which permits to compute the algebraic immunity d of a Boolean function with n variables in $\mathcal{O}(D^2)$ operations, for $D \approx \binom{n}{d}$, rather than in $\mathcal{O}(D^3)$ operations necessary in all previous algorithms. Our algorithm is based on multivariate polynomial interpolation. For assessing the vulnerability of arbitrary Boolean functions with respect to fast algebraic attacks, an efficient generic algorithm is presented that is not based on interpolation. This algorithm is demonstrated to be particularly efficient for symmetric Boolean functions. As an application it is shown that large classes of symmetric functions are very vulnerable to fast algebraic attacks despite their proven resistance against conventional algebraic attacks.

Design space exploration is an important factor in embedded systems design. During several steps in a state-of-the-art design flow, designers have to decide between many design alternatives. The decisions are lo¬ cated at various levels of abstraction. In addition, the choices affect several design goals, the alternatives therefore represent a multi-criteria decision problem. Further, the space of possible solutions is normally very large, i.e., many design alternatives exist. As a consequence, exhaustive search of the design space is prohibitive, and more sophisticated techniques have to be used to find "good" solutions. To judge the quality of a new design, the performance of a system for a given application is one core criterion. Potential performance metrics are memory demand, response time, or data throughput of an application. As a consequence, one may ask the following questions: • How can we assess the performance of a new design for a certain application? • How do we find new design points in the design space? • How can we automate the design space exploration process? In this work, we investigate several aspects of design space exploration problems and try to answer these questions. In particular, we identify and discuss the building blocks for a design space exploration framework, namely design evaluation, search strategies, and design representation. Based on these building blocks, the main contributions of this work can be described as follows: • A new hybrid method for performance evaluation of embedded sys¬ tems is presented. The new method allows the combination of exist¬ ing methods for performance analysis. In particular, these methods can be analytic or simulation-based. We provide the required inter¬ faces for this combination. • We describe a new evolutionary multi-objective optimisation algo¬ rithm, that directly incorporates the user's preferences based on performance indicators. It is easy to use and shows superior perfor¬ mance on test benchmarks and on design space exploration prob¬ lems. • A novel software framework for design space exploration is pre¬ sented. Using the framework we can re-use existing software blocks and need to implement only a few components that represent the specific problem.

This chapter introduced a framework for design space exploration of embedded systems. It is characterised by (1) multiple optimisation criteria, (2) randomised search algorithms and (3) a software interface that clearly separates problem-dependent and problem-independent parts of an implementation. In particular, the interface PISA formally characterises this separation. It is implemented in a way that is independent of programming language used and the underlying operating system. As a result, it is easily possible to extend any existing method to estimate non-functional properties with an effective multi-objective search.

Klimov and Shamir proposed a new class of simple cryptographic primitives named T-functions. For two concrete proposals based on the squaring operation, a single word T-function and a previously unbroken multi-word T-function with a 256-bit state, we describe an efficient distinguishing attack having a 232 data complexity. Furthermore, Hong et al. recently proposed two fully specified stream ciphers, consisting of multi-word T-functions with 128-bit states and filtering functions. We describe distinguishing attacks having a 222 and a 234 data complexity, respectively. The attacks have been implemented.

Design space exploration is introduced as one of the major tasks in embedded system design. After reviewing existing exploration methods at various layers of abstraction, a generic approach is described based on multi-objective decision making, black-box optimisation and randomised search strategies. The interface between problem-specific and generic parts of the exploration framework is made explicit by defining an interface called PISA. This specification and implementation interface, and the availability of a wide range of randomised multi-objective search methods, makes the proposed framework accessible to a wide range of exploration problems. It resolves the problem that existing optimisation methods cannot be coupled easily to the problem-specific part of a design exploration tool.

The analysis of real-time properties of an embedded system usually relies on the worst-case execution times (WCET) of the tasks to be executed. in contrast to that, in real world applications the running time of tasks may vary from execution to execution, e. g. in multimedia applications. The traditional worst-case analysis of the system then returns overly pessimistic estimates of the system performance. In this paper we propose a new effective method to characterize tasks with variable execution requirements, which leads to tighter worst-case bounds on system performance and better use of available resources. We show the applicability of our approach by a detailed study of a multimedia application.

This paper discusses how preference information of the decision maker can in general be integrated into multiobjective search. The main idea is to first define the optimization goal in terms of a binary performance measure (indicator) and then to directly use this measure in the selection process. To this end, we propose a general indicator-based evolutionary algorithm (IBEA) that can be combined with arbitrary indicators. In contrast to existing algorithms, IBEA can be adapted to the preferences of the user and moreover does not require any additional diversity preservation mechanism such as fitness sharing to be used. It is shown on several continuous and discrete benchmark problems that IBEA can substantially improve on the results generated by two popular algorithms, namely NSGA-II and SPEA2, with respect to different performance measures.

Scheduling on-chip resources using analytical techniques is becoming increasingly important in multimedia processing. This article presents an analytical framework for designing and evaluating schedulers for SoC multimedia platforms. The modeling technique subsumes standard event models used in real-time scheduling and accurately captures the variability in task execution requirements.

While mapping a streaming (such as multimedia or network packet processing) application onto a specified architecture, an important issue is to determine the input stream rates that can be supported by the architecture for any given mapping. This is subject to typical constraints such as on-chip buffers should not overflow, and specified play out buffers (which feed audio or video devices) should not underflow, so that the quality of the audio/video output is maintained. The main difficulty in this problem arises from the high variability in execution times of stream processing algorithms, coupled with the bursty nature of the streams to be processed. We present a mathematical framework for such a rate analysis for streaming applications, and illustrate its feasibility through a detailed case study of a MPEG-2 decoder application. When integrated into a tool for automated design-space exploration, such an analysis can be used for fast performance evaluation of different stream processing architectures.

Among the various benchmark problems designed to compare and evaluate the performance of multiobjective optimizers, there is a lack of real-world applications that are commonly accepted and, even more important, are easy to use by different research groups. The main reason is, in our opinion, the high effort required to re-implement or adapt the corresponding programs. This chapter addresses this problem by presenting a demanding packet processor application with a platform and programming language independent interface. The text-based interface has two advantages: it allows (i) to distribute the application as a binary executable pre-compiled for different platforms, and (ii) to easily couple the application with arbitrary optimization methods without any modifications on the application side. Furthermore, the design space exploration application presented here is a complex optimization problem that is representative for many other computer engineering applications. For these reasons, it can serve as a computer engineering benchmark application for multiobjective optimizers. The program can be downloaded together with different multiobjective evolutionary algorithms and further benchmark problems from http://www.tik.ee.ethz.ch/pisa/.

It is noted that network processors (NPs) generally consist of multiple processing units such as CPU cores, microengines, and dedicated hardware for computing-intensive tasks, memory units, caches, interconnections, and I/O interfaces. Following a system-on-a-chip (SoC) design method, these resources are then put on a single chip and they must interoperate in order to perform packet processing tasks at line speed. The process of determining the optimal hardware and software architecture for such processors includes issues involving resource allocation and partitioning. The chapter presents a framework for the design space exploration of embedded systems. It is observed that the architecture exploration and evaluation of network processors involve many tradeoffs and a complex interplay between hardware and software. The chapter focuses on high level of abstraction, where the goal is to quickly identify interesting architectures that can be further evaluated by taking lower-level details into account. Task models, task scheduling, operating system issues, and packet processor architectures collectively play a role in different phases of the design space exploration of packet processor devices.