Basic Local Alignment Search Tool (BLAST/BLASTP) [3], often referred to as the Google of biological research [9], is widely used to query a large database to find homologous gene/protein sequences. Though there have been attempts to accelerate BLASTP, the protein sequence alignment tool, on GPUs, they remain slower than CPU/multicore-based multi-threaded implementations. In this paper, we introduce BLAZE, a GPU-accelerated drop-in replacement for BLASTP that produces identical results while achieving speedups over both multithreaded and GPU-accelerated implementations. BLAZE achieves these speedups by diagnosing key performance challenges in the workload and applying our innovations to address these challenges. BLAZE's three key innovations include (1) hybrid (fine-grained and coarse-grained) parallelism unlike previous coarse-grained approaches which suffer from load imbalance and divergence, (2) sequence length-customized kernels unlike previous "one-size-fits-all" approaches, and (3) common-case GPU optimizations that are difficult to support in the general case. In addition to these high-level innovations, BLAZE employs a host of recent features in GPUs that enable efficient implementations of much of the BLAST processing pipeline. On an 8-core system with an Nvidia RTX 3080 (Ampere) GPU running the BLAST query benchmark suite on the 266 GB nr database, BLAZE achieves 18.2x speedup over single-threaded BLASTP, 4.8x speedup over previous GPU-accelerated baselines and 1.9x speedup on average over a 16-way multithreaded BLASTP.

Recognizing the importance of whole genome alignment (WGA), the National Institutes for Health maintains LASTZ, a sequential WGA application. As genomic data grows, there is a compelling need for scalable, high-performance WGA. Unfortunately, high -sensitivity, `gapped' alignment which uses dynamic programming (DP) is slow, whereas faster alignment with ungapped filtering is often less sensitive. We develop FastZ, a GPU-accelerated, gapped WGA software which matches gapped LASTZ in sensitivity. FastZ employs a novel inspector-executor scheme in which (a) the lightweight inspector elides DP traceback except in common, extremely short alignments, where the inspector performs limited, eager traceback to eliminate the executor, and (b) executor trimming avoids unnecessary work. Further, FastZ employs register-based cyclic-buffering to drastically reduce memory traffic, and groups DP problems by size for load balance. FastZ running on an RTX 3080 GPU and our multicore implementation of LASTZ achieve 111x and 20x speedups over the sequential LASTZ, respectively.

Convolutional neural networks (CNNs) are emerging as powerful tools for visual recognition. Recent architecture proposals for sparse CNNs exploit zeros in the feature maps and filters for performance and energy without losing accuracy. Sparse architectures that exploit two-sided sparsity in both feature maps and filters have been studied only at small scales (e.g., 1K multiply-accumulate(MAC) units). However, to realize their advantages in full, the sparse architectures have to be scaled up to levels of the dense architectures (e.g., 32K MACs in the TPU). Such scaling is challenging since achieving reuse through broadcasts incurs implicit barrier cost raises the inter-related issues of load imbalance, buffering, and on-chip bandwidth demand. SparTen, a previous scheme, addresses one aspect of load balancing but not other aspects, nor the other issues of buffering and bandwidth. To that end, we propose the barrier-free large-scale sparse tensor accelerator (BARISTA). BARISTA (1) is the first architecture for scaling up sparse CNN accelerators; (2) reduces on-chip bandwidth demand by telescoping request-combining the input map requests and snarfing the filter requests; (3) reduces buffering via basic buffer sharing and avoids the ensuing barriers between consecutive input maps by coloring the output buffers; (4) load balances intra-filter work via dynamic round-robin work assignment; and (5) employs hierarchical buffering which achieves high cache bandwidth via a few, wide, shared buffers and low buffering via narrower, private buffers at the compute. Our simulations show that, on average, barista performs 5.4x, 2.2x, 1.7x, 2.5x better than a dense, a one-sided, a naively-scaled two-sided, and an iso-area two-sided architecture, respectively. Using 45-nm technology, ASIC synthesis of our RTL design for four clusters of 8K MACs at 1 GHz clock speed, reports 213 mm$^2$ area and 170 W power.