VeSTIC (Vertical-Slit Transistor based Integrated Circuit) architecture enables easy integration of all types of transistors on the same chip. One of the elements available in this technology is Junction Vertical-Slit Field-Effect Transistor (JVeSFET). Simulation based feasibility studies indicate that the device exhibit attractive electrical properties like DC characteristics of relatively low subthreshold slope and may be considered as a good candidate for applications requiring low-noise and radiation-tolerant performance. A compact model of JVeSFET suitable for circuit simulators has been developed in this paper(1). It includes a reduced number of empirical fitting parameters and is accurate and universal enough to provide for changes of the basic material parameter of the device.

VeSTIC technology [1, 2] is a very promising concept of digital, analog and mixed mode ICs design, providing very large scale of integration, extreme layout regularity, as well as the possibility of manufacturing cost reduction and of fully three-dimensional integration. These features seem to be very attractive also in the case of MEMS systems, in particular MAP sensors. With regard to prospective applications, a first insight to noise spectra and radiation hardness of the field-effect VeSTIC devices has been performed and confirms their usefulness.

The VeSTIC technology proposed by Maly [4] seems to be very attractive for manufacturing of mixed analogue/digital circuits of highly regular layout in nanoscale. First results of a feasibility study of a new JFET structure designed in the VeSTIC 3D geometry JVeSFETs [7] are very promising and indicate good electrical properties. A preliminary compact model for circuit simulation has been presented in this paper.1

This paper presents simulated DC characteristics of deep-submicron JFETs conforming to the principle of extreme layout regularity, that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision proposed in [4]. Exploration of parameter space of this fully symmetrical dual gate JVeSFETs has been performed. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed.

This paper presents a simulation based feasibility study of deep-submicron JFETs obeying an extreme layout regularity, that is a foundation of a new Vertical Slit geometry ICs (VeSTICs) vision proposed in [4]. DC characteristics obtained for symmetrical dual gate JVeSFETs have been investigated in a wide range of bias voltages. As a conclusion an assessment of applicability of these devices in nano-size era SoCs is proposed.