Multi-step Chemical Mechanical Polishing (CMP) has been used in copper interconnect fabrication for more than a decade. During this time, advances in both the CMP-based damascene manufacturing processes and in the design flows, have enabled significant uniformity improvements for both metal thickness and surface topography, producing corresponding improvements in parametric and functional yields and enabling smaller process nodes. However, improving post CMP planarity and widening CMP process windows have lead to an increased risk of functional yield failures due to copper pooling (sometimes called puddling). These failures occur when the overburden copper and/or barrier material is not cleared during CMP, producing an electrical short between two neighboring lines. We first sought to understand the source of this failure mode, based on recently reported research and data trends seen in state of the art copper CMP manufacturing processes. Once copper pooling mechanisms were identified, CMP models were enhanced to more accurately predict pooling hotspot locations. These models can be used to improve CMP process optimization and/or Design for Manufacturing (DFM) based flows that detect and remove pooling hotspots.

The ever-shrinking lithography process window dictates that we maximize our process window, minimize process variation, and quantify the disturbances to an imaging process caused upstream of the imaging step. Relevant factors include across-wafer and wafer-to-wafer film thickness variation, wafer flatness, wafer edge effects, and design-induced topography. We present our effort to predict design-induced focus error hot spots based on prior knowledge of the wafer surface topography. This knowledge of wafer areas challenging the edge of our process window enables a constructive discussion with our design and integration team to prevent or mitigate focus error hot spots upstream of the imaging process. (C) 2010 Society of Photo-Optical Instrumentation Engineers. [DOI: 10.1117/1.3530580]

Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

Electromigration data and a theoretical model have shown that Cu lifetime in on-chip Damascene interconnect structures has dropped for every new interconnect generation, even when tested at the same current density. In addition, a mixture of bamboo and polycrystalline grain structures instead of a bamboo-like structure observed for < 90 nm wide lines (65 run technology node) resulted in further lifetime degradation by the addition of grain boundary diffusion. The techniques for improving EM lifetime either by modifying the interconnect structure by adding dummy vias on top of a Cu line, a Ru cap on the Cu top surface, or the formation of a thin CuSiN layer at the Cu/dielectric interface were investigated. The upper dummy vias, the Ru cap or CuSiN layer on the top surface of the Cu lines interrupted the Cu mass flow along the top surface interface which can improve lifetimes. The upper level dummy via structure was a powerful tool for helping to understand the Cu microstructure and to distinguish fast diffusion paths in the line.

A high performance 45nm BEOL technology with proven reliability is presented. This BEOL has a hierarchical architecture with up to 10 wiring levels with 5 in PECVD SiCOH (k=3.0), and 3 in a newly-developed advanced PECVD ultralow-k (ULK) porous SiCOH (k=2.4). Led by extensive circuit performance estimates, the detrimental impact of scaling on BEOL parasitics was overcome by strategic introduction of ULK at 2times wiring levels, and increased 1times wire aspect ratios in low-k, both done without compromising reliability. This design point maximizes system performance without adding significant risk, cost or complexity. The new ULK SiCOH film offers superior integration performance and mechanical properties at the expected k-value. The dual damascene scheme (non-poisoning, homogeneous ILD, no trench etch-stop or CMP polish-stop layers) was extended from prior generations for all wiring levels. Reliability of the 45 nm-scaled Cu wiring in both low-k and ULK levels are proven to meet the criteria of prior generations. Fundamental solutions are implemented which enable successful ULK chip-package interaction (CPI) reliability, including in the most aggressive organic flip-chip FCPBGA packages. This represents the first successful implementation of Cu/ULK BEOL to meet technology reliability qualification criteria