Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.

We propose an approach for reduction of the contact resistance by inducing dielectric breakdown in a Si-dielectric-metal contact stack. We observe a 36% reduction in the contact resistance as well as an improvement in the uniformity in the distribution after dielectric breakdown. The results open up interesting device applications in complementary metal oxide semiconductor technology.

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρc) extraction of 2×10-8Ω cm2 and 5×10-9Ω cm2 for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρc values. The results show the importance of such test structures to accurately extract ultralow ρc values relevant to sub-14-nm technology nodes.

High mobility materials (such as SiGe, Ge and III-V) are attractive replacements for the conventional Si channel material in future CMOS technology nodes (<11nm) to improve performance and reduce power. To control short channel effects at these aggressively scaled device geometries, non-planar multi-gate devices will be needed. Although progress has been made in high mobility non-planar devices with SiGe, Ge and III-V channel materials, significant integration challenges remain. In this paper, the opportunities of non-planar non-Si CMOS and the hetero-integration challenges of high mobility material epitaxy on Si are discussed.

The impact of NiPt thickness scaling on total resistance is investigated using short-channel (L-g = 40 nm) nm high-k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm ("planar single-gate thin-body FD SOI FET") to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a > 2x (NFET) and > 6x (PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs.

We introduce a figure of merit (FoM) to quantify RRAM read current instability, a complex multi-level RTN-like signal, generally observed in read current. Log(FoM) follows a normal statistical distribution describing the probability of occurrence of a read current fluctuation of a given amplitude. We demonstrate that peak-to-peak RTN amplitude decreases with the reduction of the read current that enables scaling down RRAM operating currents. The developed statistical model for the read instability allows to estimate the maximum size and minimum operating current for reliable operations of high density RRAM array.

We have developed novel real-time methodology to determine intrinsic forming and switching characteristics of HfOx based RRAM. Elimination of parasitics in 50nm × 50nm cross-bar 1T1R devices (Cp<; 50fF) integrated on 300mm wafers using fab-friendly TiN electrodes enabled superior control of high and low resistance of a conductive filament (CF). Sub 50fF parasitics also critically enable a pulsed forming method compatible with high volume manufacturing (HVM). A novel assessment of RRAM operation trade-offs is also made. For example, the trade off in set/reset voltage tuning, variability, current and speed is determined. These trade-offs are significant to quantitatively assess intrinsic potential and limitations of HfOx based RRAM for future memory applications.

Double-gate FinFET (110) (110) and (100) (100} electron mobility (μ e ) and hole mobility (μ h ) are experimentally investigated for the following: 1) a wide range of boron and phosphorus fin doping concentrations and 2) a wide variety of gate stacks combining HfO 2 , SiO 2 , or SiON insulators with TiN or poly-Si electrodes. It is found out that, irrespective of fin doping and gate stack, (110) (110) μ e is competitive with the (100)(100) μ e , while (110)(110) μ h is ≥ 2× higher than (100) (100) μ h . Inversion μ e and μ h are independent of doping as long as the effective field/doping combination enables the screening of the depletion charge. Mobility degradation with doping is significantly lower in accumulation mode (AM) than in inversion mode (IM) such that, for heavily B-doped fins, AM hole mobility exceeds the IM electron mobility even in (100) FinFETs. In undoped fins, ALD TiN gate stress is observed to improve μ e for both orientations without degrading μ h .

We demonstrate statistically significant data for specific contact resistivity (rho(c)) of sub-10(-8)Omega-cm(2) and sub-2x10(-8)Omega-cm(2) for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small rho(c) range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the rho(c) as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications.

Capacitance–voltage measurements are performed on sub-100nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.

We demonstrate for the first time, a 20nm FinFET using a new, conformal, and damage-free monolayer doping technique. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable an ultra-shallow (X j ~5nm) and abrupt (0.6nm/dec) junction formation around a high aspect ratio fin structure, which overcomes the possible FinFET pitch scaling limitations of traditional doping techniques. FinFETs featuring MLD junctions were successfully demonstrated with good electrostatics control down to a gate length of ~40nm. With further scaling of the fin width, sub-threshold swing and threshold voltage roll-off can be further improved. This low damage and conformal doping is a promising technique to address key FinFET scaling issues associated with parasitic series resistance and short channel control for the 15nm node and beyond.