computer architecture, memory hierarchy, caches, DRAM, burst buffer, compiler, SUIF, performance, low cost This paper describes a novel memory interface architecture, called burst buffers. Although simple, it regularly attains more than a factor of two improvement in performance for media algorithms above a normal data cache using conventional DRAM technology. This paper shows that exposing the features of main memory permits architectural and compiler innovations. Performance gains are achieved by improving the use of available bandwidth from DRAM by utilising three techniques: long bursts, burst pipelining and buffer re-use. This paper demonstrates the benefits of the new memory interface architecture when included in an embedded system alongside the data cache. This interface adds little or no extra system cost.

Moving resource management out of the operating system kernel facilitates a high degree of customisation. The lowest layer of the Arena system provides an abstract interface to conventional processor hardware (Mayes, 1993; Quick, 1995). The idea is to encapsulate the hardware behind an interface with certain low-level concepts which are generally applicable to any processor. Localization of hardware-dependency has the effect of increasing modularity and thus portability. This encapsulation, termed the Arena hardware object (HWO) supports portable user-level customizable resource management (Mayes et al., 1994). The aim is to remove resource management policy from the HWO whilst maintaining its integrity. The present paper deals with the Arena approach to the provision of pure user-level threads. Native implementations on Sparc and i486 processors are briefly described and performance figures are given. The compromise between reducing policy and maintaining integrity in the HWO implementations is discussed.

General-purpose operating systems, such as UNIX, which evolved on single processor machines, have made the transition, in one form or another, to parallel architectures (e.g. Rothnie, 1992; Holman, 1992). However, it is not clear that all users of parallel architectures require the virtual machine presented by a general-purpose operating system (e.g. Bryant et al., 1991). It is unfortunate if such users are given the alternatives of either compromising with whatever operating system interface is available, or writing all the low-level routines for themselves. One solution to this problem is to provide customisable systems, so that for high performance, parallel applications acquire a tailored resource management environment (e.g. Mukherjee and Schwan, 1993). This paper first gives some background to applications and operating systems, and then describes a flexible and extensible system currently being developed.