RO4396686 is a small molecule KDR, FGFR, and PDGFR inhibitor with good pharmacokinetic properties in rodents. In a mouse corneal neovascularization assay, this compound inhibited VEGF-induced angiogenesis. Tested in a H460a xenograft tumor model this agent effected significant tumor growth inhibition at doses as low as 50 mg/kg.

(+/-)-1-(anti-3-Hydroxy-cyclopentyl)-3-(4-methoxy-phenyl)-7-phenylamino-3,4-dihydro-1H-pyrimido[4,5-d]pyrimidin-2-one (RO4383596) is a potent and selective inhibitor of the pro-angiogenic receptor tyrosine kinases KDR, FGFR, and PDGFR. This agent has an excellent pharmacokinetic profile and is highly efficacious in rodent models of angiogenesis upon oral administration.

This paper introduces a new approach to testing a basic analog-only delay-locked loop (DLL) that is embedded in a field-programmable gate array, an application specific integrated circuit, or a system-on-chip (SoC). Part of the DLL circuitry is duplicated and then connected to the DLL in a way that produces a replica of the control voltage. This shadow of the control voltage is used to measure the loop's response to a step in phase. The concept of test construct (TC) gain is introduced as a means of improving detectability. The benefit of the testing approach is demonstrated by injecting defects into the DLL and detecting them through the TCat the observation point.

With the increasing use of phase-locked loops (PLLs) embedded in FPGAs, ASICs, and system-on-chip (SOC), there is a growing need for methods to verify their operation. This paper describes a general and organized list that includes tests for lock, jitter, stability, and modulation response. The list is offered as a guide to the verification and testing of an embedded PLL. For that reason, it is presented in such a way as to allow the reader to determine the extent to which the verification will be carried out The tests are covered from the easiest to the most complicated to perform, with the amount of information gathered increasing along,with the complexity of the test.

With the increasing use of Phase-locked loops (PLLs) embedded in FPGAs, ASICs, and System-On-Chip (SoC), there is a growing need for methods to verify, their operation. This paper describes a general and organized list that includes tests for lock, jitter, stability and modulation response. The list is offered as a guide to the verification and testing of an embedded PLL. For that reason it is presented in such a way as to allow the reader to determine the extent to which the verification will be carried out. The tests are covered from the easiest to the most complicated to perform, with the amount of information gathered increasing along with the complexity of the test. The paper also discusses the difference between observing a stand-alone PLL and an embedded PLL

With the increasing use of phase-locked loops (PLLs) embedded in FPGAs, ASICs, and Systems-On-Chip (SOC), there is a growing need for methods to verify their operation. This paper describes a coherent list, which includes tests for lock, jitter, stability, and modulation response. The information is offered as a guide to the verification and testing of an embedded PLL. For that reason it is presented in such a way as to allow the reader to determine the extent to which the verification will be carried out. The tests are covered from the easiest to the most complicated to perform