This paper addresses the generation of behavioral models of digital ICs for signal and power integrity simulations. The proposed models are obtained by external port measurements and by the combined application of specialized state-of-the-art modeling techniques. The proposed approach is demonstrated on the I/O buffers and the core power supply ports of a commercial 90 nm flash memory.

This paper focuses on the power delivery characterization of high-speed IC memories by means of on-chip measurements. A systematic analysis of the measurement setup, of the effects of chip biasing and of the use of the measured responses to develop models defined by simplified circuit equivalents is given. All the results collected in the paper are based on real measurements carried out on a commercial 90nm flash memory.

This paper describes the research activity that is being carried out in the MOCHA project, a cooperative R&D effort at the European scale. The aim of the project is to develop reliable modelling and simulation solutions for SiP design verification.

A NOR Flash memory fully functional at 1 V is demonstrated, based on an inductor built directly into the package. A ferromagnetic nucleus is wound by means of the bonding wires and the first package substrate metal layer. The magnetic field does not affect the system since it is strictly confined into the toroidal nucleus. The whole system is enclosed into a standard BGA package 8 x 14 x 1.4 mm with 88 balls.

The PoP (Package on Package) design procedure is described in this paper, focusing principally on the constraints and the system characteristics. The PoP structure is more and more diffused because it increases the customer flexibility and the final yield by means of a separate testing of Top and Bottom devices. In this paper, a Top PoP design, composed by two stacked memory dice (a NOR Flash and a SDRAM), is described pointing out the electrical package impact. The memory PoP has to be accessed up to 250 Mb/s. Such a frequency involves the package to be designed basing on some rules and evaluating its electrical impact by means of a signal integrity flow.

A NOR Flash memory system, the supply voltage of which can be as low as 1.2 V, is described. The internal memory chip supply voltage (1.8 V) is obtained by means of a DC-DC converter totally included in the same package of the memory. This system represents a way to overcome technology limitations to generate a Flash device supplied at a voltage close to 1 V and below. The NOR Flash memory system is assembled in a ball grid array 88 balls 14 x 8 x 1.6 mm, with the same ballout of the standard Flash memory working at 1.8 V.