Usually, the routing process is made by non-specialists in electrical simulation that only meet the requirement of the standards. The aim of this work is to supply a new tool dedicated to assess the quality of the tree network routing. An innovative modeling method of advanced unbalanced interconnections called “comb tree” for distributing high speed clock signals is featured. The flow work summarizing the routine process of new design rule is established to enhance the performance of advanced packages for high speed circuits. The analytical approach for extracting the voltage transfer function corresponding to the electrical signal paths in function of tree branch parameters is fundamentally inspired from SIMO/SISO electrical circuit analogy. Doing so, the wideband characteristic impedances and propagation constants of elementary lines constituting the tree are extracted from geometrical and physical properties. A PCB prototype of unbalanced comb tree network over FR-4 substrate has been designed and manufactured for the experimental verification. Then, frequency analyses of different VTFs have been carried out. Less than 1dB of error has been found within the DC-3GHz bandwidth and less than 4 dB within 3-10GHz. In addition, time-domain analyses with 2 Gbps input signal has been realized. Excellent agreements between transient simulations and the proposed model have been established. The model developed is potentially useful for predicting the signal integrity and optimization process of unbalanced advanced PCB and on-chip tree interconnects.

A distributed behavioral model of two-level 1:n (1-input and n-outputs) asymmetrical interconnect tree network is explored. Based on circuit approach, theoretic analysis illustrating the mechanism of the underlying model extraction is described. The asymmetrical tree model is yielded from an innovative single input multiple output/single input single output (SIMO/SISO) transform. For predicting the signal responses each outbranch of the tree, the voltage transfer function (VTF) corresponding to any electrical path from the input to the output node under interest is mathematically expressed. To verify the relevance of the behavioral method proposed, 1:3 asymmetrical two-level distributed tree network was designed in microstrip planar circuit. Then, numerical validations were performed both in the frequency- and time-domains. It was pointed out that good accordance between the VTF frequency responses of tested tree signal paths from DC to 4GHz was confirmed. The behavioral two-level model developed is benefited not only in term of simplicity and computation speed but also to its flexibility to complex shape of asymmetrical interconnect trees. The model could be useful for the high-speed electronic circuit manufacturers for predicting the signal integrity through interconnect PCB trees.

A predictive signal integrity (SI) model of coupled PCB interconnects for high-speed application is stated. It is derived from the analytical modeling of coupling matrices between neighboring transmission lines (TLs). The overall ABCD matrix is regenerated and manipulated by using the modal approach. Afterwards, the S-parameters of the structure are substantially extracted for forecasting the behavior SI propagating along the underlying interconnections. In order to reveal the effectiveness of the fast model developed, EM/circuit co-simulations with commercial tool were performed both in the frequency- and time-domains with 1Gbps-rate-mixed signals. Different configurations were undertaken. The validity of the centimeter length coupling model hereby with respect to the geometrical parameters of the interconnect structures is also investigated. Finally, potential applications for high-speed systems are discussed, especially for non-symmetrical coupled lines and microelectronic interconnects.

This paper presents an enlarged study about the 50-% propagation-time assessment of cascaded transmission lines (TLs). First and foremost, the accurate modeling and measurement technique of signal integrity (SI) for high-rate microelectronic interconnection is recalled. This model is based on the reduced transfer function extracted from the electromagnetic (EM) behavior of the interconnect line RLCG-parameters. So, the transfer function established takes into account both the frequency dispersion effects and the different propagation modes. In addition, the transfer function includes also the load and source impedance effects. Then, the SI analysis is proposed for high-speed digital signals through the developed model. To validate the model understudy, a prototype of microstrip interconnection with w = 500 µm and length d = 33 mm was designed, simulated, fabricated and tested. Then, comparisons between the frequency and time domain results from the model and from measurements are performed. As expected, good agreement between the S-parameters form measurements and the model proposed is obtained from DC to 8 GHz. Furthermore, a de-embedding method enabling to cancel out the connectors and the probe effects are also presented. In addition, an innovative time-domain characterization is proposed in order to validate the concept with a 2.38 Gbit/s-input data signal. Afterwards, the 50-% propagation-time assessment problem is clearly exposed. Consequently an extracting theory of this propagation-time with first order RC-circuits is presented. Finally, to show the relevance of this calculation, propagation-time simulations and an application to signal integrity issues are offered.

This paper is devoted to investigating experimental validations of a simple modeling method of PCB interconnects for high-speed signal integrity and electromagnetic compatibility applications. Based on the theoretical approach using the extraction method of the interconnect per-unit-length RLCG parameters, the reduced models of the corresponding transfer function, -parameters, and access and transfer impedances are also established. The methodology describing the different steps of the technique proposed for practical use cases in ultra wideband is established. To verify the effectiveness of the concept under consideration, time-domain validations from the frequency-measured data are realized by using printed circuit board microstrip interconnect lines with micrometers width and millimeters long. Therefore, the model was first validated experimentally, and with electromagnetic simulations, in frequency domain via comparison of -parameters and -matrix from dc to some gigahertz. It was found that relative errors lower than 1 dB were evaluated between the insertion loss of the models, simulations, and measurements. Then, by injecting noisy digital- and mixed-signals with 1 Gigasymbol/s, relative errors of lower than 1% were evaluated by considering the time-domain responses. Compared to the existing interconnect modeling tools, the developed one presents a high accuracy, simplicity, and very less computation time.

ABSTRACTThe H‐tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra‐wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H‐tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of two‐ and three‐level tree networks were performed. Distributed H‐tree realistic devices formed by sub‐millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input. Copyright © 2012 John Wiley & Sons, Ltd.

This paper is devoted on the characterization method of RF/digital PCB interconnections for the prediction of the highspeed signal transient responses. The introduced method is based on the use of the interconnection line RLCG-model. Theoretical formulae enabling the extraction of the electrical per-unit length parameters R, L, C and G in function of the interconnection line physical characteristics (width, length, metal conductivity, dielectric permittivity ... ) are established. Then, by considering the second order approximation of the interconnection RLCG-model transfer matrix, the calculation process of the transient responses from the interconnection system transfer function is originally established. To demonstrate the relevance of the proposed model, microwave-digital interconnection structure comprised of millimetre microstrip line driven and loaded by logic gates which are respectively modelled by their input and output impedances was considered. Then, comparisons between the SPICE-computation results and those obtained from the proposed analytical model implemented in Matlab were made. As results, by considering a periodical square microwave-digital excitation signal with 2 Gbits/s rate, transient responses which are very well-correlated to the SPICE-results and showing the degradation of the tested signal fidelity are observed. The numerical computations confirm that the proposed modelling method enables also to evaluate accurately the transient signal parameters as the rise-/fall-times and the 50% propagation delay in very less computation time. For this reason, this analytical-numerical modelling method is potentially interesting for the analysis of the signal integrity which propagates in the high-speed complex interconnection systems as the clock tree distribution networks. In the continuation of this work, we would like to apply the proposed modelling process for the enhancement of signal quality degraded by the RF/digital circuit board interconnection where the signal delays and losses became considerably critical.

The paper presents a reduced modeling method of a microstrip interconnect for the signal integrity (SI) applications. First-and second-order polynomial models of interconnects based on distributed RLCG model of a transmission line are investigated. Model accuracies are compared with exact circuit/EM co-simulations for a typical high-speed 20 mu m-wide microstrip interconnect on Alumina substrate for varying interconnect lengths between 1 and 10 mm and for signal data rates between 1 and 10 Gbit/s. It is shown that the second-order model has a relative amplitude and phase errors lower than 1% from DC to 40 GHz. Also, the second-order model predicts very well the time-domain response to a pulse signal, making it suitable for the accurate prediction of the degradation of RF/digital signals in the high-speed integrated systems.

This paper is devoted to the extension of the interconnect effect equalization concept with NGD circuits for UWB applications. First, RC interconnect effects are considered. It was found that by cascading with the NGD structure, the propagation delay of the considered rate 4 Gbps signal was compensated for about 98-%. Then, the feasibility of the technique by taking into account the interconnection inductive effect with RLC-model is also investigated. It was demonstrated that the technique proposed brings opportunities to compensate for simultaneously the propagation delay and distortions. Then, the application of the proposed technique for the optical interconnect correction is discussed.

SUMMARYThis article presents a modelling method of the signal delays induced by microelectronic interconnections regarding RL impedance load. The method proposed is based on the RLC model of the transmission lines (TL) extracted from the equivalent S parameters. Formulation for estimating the interconnection propagation delay is established according to the behaviour of the TL unit step responses. The second order model is validated with a microstrip interconnect prototype with simulations and measurements in frequency and time domains. The developed propagation delay model was validated with SPICE computations. For that, a transient simulation was performed by considering input signals corresponding to high‐speed data of some Gbits/s. Then, accurate results were found for interconnections with different lengths in order of millimetre and also by varying the load values. It was shown that the computed 50% propagation delays present of relative errors about 5%. Copyright © 2011 John Wiley & Sons, Ltd.