As the automotive industry transitions toward electric and autonomous vehicles, the reliability and availability of low voltage (LV) power systems become increasingly critical, particularly for safety-related functions. Current on-board architectures typically use a high voltage (HV) battery for traction and high-power loads, while a separate LV battery remains essential for LV auxiliaries, autonomous driving, and safety-critical systems. To enhance system reliability and reduce dependence on bulky LV energy storage, this paper presents the concept, design, and control of a redundant and fault-tolerant isolated three-port DC-DC converter for HV to LV on-board power supply systems in electric vehicles (EVs). The proposed topology enables power sharing, redundancy, and fault tolerance, allowing a significant reduction in LV battery capacity and the potential elimination of traditional lead-acid technology.

The modular multilevel multi-port solid-state transformer is an attractive topology for simultaneously interconnecting and managing bidirectional power transfer among the MVAC grid, the MVDC grid, and the LVDC bus, thus providing a high degree of operational flexibility. Identical isolated DC-DC converter stages incorporating medium-frequency transformers are integrated into the submodules to achieve the required voltage conversion and galvanic isolation between the medium-voltage and low-voltage sides. This paper outlines the fundamental operating principles and system-level control strategies using an analytical average model. A novel energy balancing method exploiting the isolated DC-DC converters is proposed. Finally, the converter’s operating behaviour, along with the proposed control strategies and energy-balancing methods, are verified using time-domain simulations of the switched model for a 2 MVA system.

The modular multilevel type multi-port solid-state transformer (SST), is a promising topology to connect and control the bidirectional power flow among the MVAC grid, the MVDC grid, and LVDC bus simultaneously and with full degree of flexibility. Identical monolithic isolated DC-DC converters containing medium-frequency transformers are thereto embedded in the submodules to provide voltage conversion and galvanic isolation between medium-voltage and low-voltage sides. This work introduces a medium-voltage battery energy storage variant with battery packs directly integrated into each cell of the system. The basic operating principle and system control is discussed based on an analytical average model. And performance of the approach is demonstrated by simulations. Special focus is put on energy balancing control between the MMC cells, where leg circulating currents of the MMC are used. Finally, the converter operation, proposed energy balancing methods and control approaches are validated by simulation of the average model of a 3 MVA, 4kV MVAC, 8kV MVDC and 1500V LVDC system.

Triangular current mode (TCM) enables the benefit of zero voltage switching, but it is accompanied by two significant functional limitations. Initially, it often requires expensive FPGA, ASIC, and/or specialized hardware-based sensing. Secondly, the time delays linked with such sensing and processing can lead to a trade-off between the achievable switching frequency and the precision of the triangular inductor current waveform. This paper delivers the experimental verification of an alternative method where the inductor current envelopes are measured using straightforward analog quasi-peak detectors. The sampling rate needed for these envelopes is in first approximation independent of the applied switching frequency. The control behavior is mainly unaffected by time and signal delays due to the low frequency envelope signals being used, allowing for an affordable standard DSP to implement the proposed method. Importantly, the same control loop can also facilitate continuous conduction mode (CCM) operation, whereby a normal CCM operation at constant switching frequency and a mode with variable switching frequency and constant ripple current can be featured. Using a standard two-level grid-tied inverter configuration as a case study, this paper shows a measurement based verification of the concept of the envelope tracking-based TCM (E-TCM) and CCM (E-CCM) method. A prototype is presented to demonstrate the behavior of an envelope tracking hardware solution, including a measurement-based evaluation of the proposed circuits in operation with a 0.5 kVA, two-level SiC-based converter. This converter, together with its envelope tracking circuit, is capable of operating in TCM at frequencies up to several hundred kHz and can dynamically transition to CCM during operation.

The totem-pole PFC stage is a commonly used and widely accepted topology in industry. With the newest emerging power semiconductor technologies, such as the M-BDS, different concepts like the HERIC PFC converter are becoming increasingly more attractive and provide numerous benefits. The presence of a bidirectional switch in the HERIC converter results in a symmetric structure and avoids a problem of the totem-pole topology, the unfolding. This leads to improved performance in terms of conducted common-mode emissions and to lower control complexity. This paper presents a detailed analysis of both topologies, examining and comparing their performance in terms of conducted electro-magnetic interferences. The influence of the design aspects of the magnetic components, i.e., the grid-side boost inductor, is considered, highlighting that the conducted emissions can be effectively mitigated by a proper balancing and coupling strategy. The measurement-based evaluation utilizes a hardware demonstrator that can be operated as HERIC or totem-pole-PFC stage and fully demonstrate the effectiveness of the proposed solution, with CM noise reductions of up to 30 dB.

Typical DC-bus stabilization for low-voltage power circuits consists primarily of ceramic capacitors due to the capacity density and low equivalent series resistance (ESR) resulting in low conduction losses. Particularly in hard-switching and hard-commutation operation, the low ESR and high equivalent series inductance (ESL) of the capacitors in the commutation path restrict the damping of the switch node voltage overshoot and introduce high-frequency ringing, reducing the voltage margin of the transistor. Therefore, this paper analyzes the impact of the DC-bus impedance and proposes a DC-bus snubber based on an RC network to form the DC-bus impedance’s characteristic, which minimizes the overshoot voltage. A comprehensive simulation using measurement-derived component models is shown, which is verified by an in-situ measurement on a test PCB. Furthermore, transient measurements using a double pulse test setup show the effectiveness of the proposed approach.

A three-phase ac-dc converter with high-frequency isolation can be realized as a phase-modular system by using three single-phase Power Factor Correction (PFC) rectifier modules with isolated dc-dc converter output stages, which advantageously allows to cover a wide input voltage range by module reconfiguration from a star-(Y)- to a delta-( $\Delta $ )-arrangement. However, the main limitation of a phase-modular topology is the fact that the input power of each PFC rectifier module pulsates at twice the mains frequency such that large dc-link capacitors are required. Recent literature predicts a substantial single-phase power pulsation reduction enabled by means of third-(3 $^{\mathrm{ rd}}$ )-harmonic common-mode (CM) voltage (Y) or current ( $\Delta $ ) injection modulation. This paper experimentally verifies and extends the dc-link energy storage requirement reduction of the 3 $^{\mathrm{ rd}}$ -harmonic injection modulation concepts: In a first step, the derivation of the harmonic injection concept is recapitulated and suitable control methods are discussed for both CM voltage (Y) and CM current ( $\Delta $ ) injection. Further, an alternative CM voltage injection strategy with simplified reference generation based only on the instantaneous grid voltage measurements is presented and compared to the pure 3 $^{\mathrm{ rd}}$ -harmonic injection modulation. Measurement results obtained from a 6 kW prototype reveal a dc-link voltage variation and/or energy buffering reduction by up to 38.6 % enabled by the harmonic injection modulation compared to conventional operation without 3 $^{\mathrm{ rd}}$ -harmonic injection modulation.

Multiport power conversion topologies provide the capability of multiple independent converters with a single transformer having multiple windings (i.e., ports) potentially increasing power densities and enabling flexible (and bidirectional) power routing. In automotive onboard charger (OBC), the multiport approach combined with symmetrical series resonant circuits, the so-called multiport series resonant converter (MSRC), allows for a galvanic isolated connection between all ports: the grid-side converter (i.e., usually an AC/DC power factor correction (PFC) stage), vehicle’s main and the auxiliary low-voltage (LV) battery. The variation of the battery voltage significantly affects the MSRC operation, particularly for light loads at a low state-of-charge, and high losses can be experienced since zero-voltage-switching (ZVS) conditions are lost. In addition to the conventional control approach of the MSRC, where the power flow is set with a phase-shift between the individual full bridges or by changing the switching frequency, this paper proposes a novel and coordinated approach, including the manipulation of both and the additional modulation of the duty cycle as a function of the DC-link voltages, aiming to introduce a zero-voltage interval on the full bridge output voltages. A full mathematical description of the adopted converter topology is provided, including accurate simulation models that allow a comparison between the proposed duty cycle mode and the conventional control strategy. A detailed description of achieving ZVS within the connected full bridges is also included. Experimental results validate the proposal and demonstrate significant efficiency improvements compared to standard control approaches.

Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e., by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically $400 \,{\rm {V}}$ (for a grid with $230 \,{\rm {V}}_{\rm{rms}}$ line-to-neutral voltage) allows to employ high performance $600 \,{\rm {V}}$ power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several $100 \,{\mu }{\rm{F}}$ for a $6 \,{\rm{kW}}$ system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement $ {\Delta} {E}_{\rm{dc}}$ can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this article identifies the optimal CM voltage waveform with respect to minimizing $ {\Delta} {E}_{\rm{dc}}$ , i.e., reducing $ {\Delta} {E}_{\rm{dc}}$ to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a $6 \,{\rm{kW}}$ prototype system yield a reduction in $ {\Delta} {E}_{\rm{dc}}$ by up to $42{\%}$ (compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as $285 \,{\rm {V}}$ (i.e., below the $325 \,{\rm {V}}_\mathrm{pk}$ grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated.

Soft-switching bridge-legs facilitate high-efficiency three-phase PV inverters or PFC rectifiers. By extending a half-bridge with a resonant auxiliary circuit, including two additional transistors, zero-voltage switching (ZVS) of the main transistors can be realized (Active Resonant Commutated Pole, ARCP). Alternatively, a similar T-type bridge-leg structure achieves ZVS by operating the output filter inductor with a sufficiently high current ripple (with 3-level Triangular Current Modulation, 3L-TCM). We provide a comparative evaluation of these two concepts for the realization of 2.2 kW (per phase), 800 V DC bridge-legs with latest-generation 1200 V and 650 V SiC MOSFETs, discussing chip-area optimization, filter design for compliance with current and future EMI limits, and qualitative limits and design criteria. The calculated loss-vs.-volume Pareto fronts indicate advantages for the 3L-TCM approach, with peak switching frequencies of 72 kHz or 144 kHz and an efficiency (semiconductors and EMI filter) of about 99.6 %. The ARCP concept seems more suitable for applications that do not necessarily require EMI filters but benefit from limited switch-node $dv/dt$ (in the order of 1.5 V/ns) such as variable-speed drives.

Growing expectations of modern onboard chargers for bidirectional power, galvanic isolation and additional low voltage output(s) leads to ever-increasing part count and complexity. Nevertheless, this paper shows that very high power density can still be achieved with a multiport series resonant topology. Close to 4 kW/dm3 (excl. housing) is achieved for 7kW and 11kW applications with a charging efficiency >97% while meeting most safety and EMI standards resulting in up to 3.1 kW/dm3 (incl. housing) when liquid cooling is used. An overview of the proposed topology and optimization approach is given followed by a description of both prototypes with comparison to state of the art.

This paper presents an approach for reproducing key characteristics of non-linear, high frequency switching transients using a multilayer perceptron neural network. Training data is generated using variable time-step transient simulations of a half-bridge switching cell of SPICE transistor models together with constrained yet randomized combinations of DC-link voltage, drain currents and lumped loop inductances. Using the example of peak turn-OFF voltage overshoot for SiC and Si power transistors, the multilayer perceptrons show a mean error of less than (0.9 ± 1.3)%. The predictions of the multilayer perceptron are then compared to preliminary measurements made using a SiC half-bridge test-bench where good agreement is observed especially for higher drain currents. With continued development, such a neural network could be used in coarse, fixed-time-step simulations of any “half-bridge-based” circuit to offer typically unavailable high-fidelity information with negligible computation time. For example, a designer could choose a transistor and quickly see the limits on allowable loop inductance to avoid excessive voltage overshoot for their simulated current waveforms, or see an estimate for voltage overshoot if the loop inductances are known.

For many power converter topologies, triangular current mode (TCM) operation can offer zero voltage switching at the expense of slightly higher conduction losses but with two important practical limitations. Firstly, implementing TCM often requires a costly FPGA or an application specific integrated circuit and/or custom hardware-based sensing. Secondly, the reaction and propagation delays of such sensing and signal processing can introduce a trade-off between the achievable switching frequency and achievable precision of the controlled triangular inductor current waveform. This paper proposes an alternative approach whereby the positive and negative envelopes of the inductor current are captured using simple analog quasi-peak detectors. The sampling rate needed for the envelopes can be far slower than the switching frequency yet precise TCM operation with zero voltage switching can be ensured by means of an appropriate control scheme easily implemented using a comparatively cheap digital signal processor. Advantageously, the same control loop can also enable continuous conduction mode operation. Using a common two-level grid-tied-inverter topology as an example, this paper details the principle of the proposed envelope tracking based TCM (E-TCM) method and provides a simulation based evaluation of control error and bandwidth compared to zero-current-crossing-detection based TCM and a hysteresis based TCM. Different current sensing techniques such as hall sensors and current shunt resistors were taken into account and the simulated sensing circuitry is based on verified measurement data. With realistic signal sensing and processing delays considered, the proposed E-TCM exhibits more than 5x less distortion on the reverse current used for ZVS in the highest switching frequency regions.

The three port series resonant converter (3pSRC) is a promising topology especially for grid applications and onboard chargers. It offers galvanic isolation, high efficiency and enables a power dense design via the common multiport transformer structure. Typically, power flow is controlled by means of the switching frequency and/or the relative phase between the excitation of each transformer port. However a unique solution for the optimal combination of control variables for any unique set of port voltages and powers is non trivial. This paper proposes a control loop for naturally approximating such optimal control variables. The mathematical model used for calculating the power flow between the three ports is presented and a method for finding the switching frequency that best balances zero-voltage-switching (ZVS) and high efficiency for a given operation point is given. The control approach is demonstrated with a Silicon Carbide (SiC) based prototype for an on-board charger application.

This paper shows two fast algorithms that when combined, enable inductor volume and loss estimation based only an inductance value and an arbitrary steady-state current waveform. Together, these two algorithms offer an easily accessible way to include magnetic components into multi-objective-circuit-simulation-level topology optimizations for power density, without any reliance on big component/material databases or artificial intelligence approaches. The first algorithm is based on an existing method for finding the optimum number of windings for an inductor, but is expanded here to include DC-bias dependent Steinmetz Parameters. This is initially demonstrated with a precise numeric solution before being reduced to a faster analytic approximation that yields excellent agreement. The second algorithm finds the optimal geometric scaling of a reference core by equating power losses with thermal power dissipation to ensure maximum power density. The algorithms are applied in simulation to a Monte-Carlo optimization of a buck circuit, where the resulting inductor and topology design is fabricated in hardware. The efficiency is measured and compared to the predictions from the circuit optimization.

A frequency-elastic drive mode for a sucker rod pumping system is introduced to reduce its polished rod peak loads and the total energy consumption. Numerical modeling and an extensive field test verify the concept. The frequency-elastic drive mode is a software solution for variable speed drive systems, which can be applied in the controller and does not require any hardware adjustments. The novel drive mode adjusts the set frequency, sent by the controller to the frequency converter, depending on the actual power requirements. An increase in power consumption results in a reduction of the set frequency, which is proportional to the power consumption increase. A reduction in power consumption results in the opposite effect to achieve a similar pumping speed as for regular operation. The frequency-elastic drive mode is simulated by a numerical model, which covers the entire pumping system. An extensive field test was performed to verify the concept and the numerical model. The simulation and the field test have confirmed the concept of the frequency-elastic drive mode and quantified its saving potential. The evaluation of the field test has shown that the energy-saving potential can reach five percent. In addition, a peak polished rod load reduction of up to three percent was seen. At the tested pumping system the frequency elastic drive mode under optimized parameters yields the best results in terms of total energy savings in the pumping speed range between 7 to 10 strokes per minute. A downhole system efficiency increase was seen for any pumping speed. The numerical model matches the field test data and allows the performance prediction of the novel drive mode for changed parameters and wellbore configurations without extensive field testing. The novelty of the presented paper is the concept of the frequency-elastic drive mode, which is a pure software solution for variable speed drive sucker rod pumping systems. The holistic model includes the entire pumping system and matches the field test data at remarkable accuracy.

In contrast to common 3-phase topologies, DC-link capacitance can be reduced by combining input power after the DC-link using a multi-port transformer and suitable control. Initial results of this approach demonstrate stable 12 kW output power using only 5 μF DC-link capacitance per phase, promising higher power density and reliability. Furthermore, a novel control scheme is proposed that allows high frequency reactive power flow through the multi-port transformer to be manipulated via gate-signal phase angles, in order to achieve maximum efficiency and minimum DC-link voltage ripple for any load condition.

Pre-charging of DC-link capacitors limits the inrush current when connecting a power converter to the grid. In its simplest form, this can be realized with a relay parallel to a resistor and a diode as shown in [1] and [2]. This digest proposes an alternative approach for automotive onboard battery chargers that removes any need for such dedicated pre-charging hardware and completely avoids inrush currents. Instead, by exploiting the massive difference in energy storage between the main battery and the DC-link, the energy needed to pre-charge the DC-link capacitor can be reliably obtained using reverse power flow from the main battery through the isolating transformer, even if the main battery were to be almost entirely discharged. Furthermore, this paper shows methods how the battery and DC-link current can be easily limited with variable frequency control or varying duty cycle at constant frequency of the CLLLC output voltage when starting to charge an empty DC-link capacitor. Experimental verification of the control approach is done and it is shown that a charging time smaller than one second is possible.

Thermal management becomes critical as loss-related component parameters become more highly temperature dependent. Although thermal simulation based on component losses is common, this work proposes closing the loop between electrical and thermal simulations with a transient system-level approach; enabling temperature dependent component parameters during circuit simulation. For a boost converter, the overall system efficiency and component losses are estimated by combining circuit simulation with the corresponding temperature distribution calculated with transient 3D-FVM. Simulations demonstrate how the overall system efficiency is influenced by the component temperature, especially during transient processes e.g. the system start up. Using the proposed co-simulation approach the temperature on one semiconductor surface could be estimated with good accordance to measured temperatures (+3.1 %/2.68 °C) during 60 s of transient start up.