This paper presents a high-throughput and reconfigurable processor for fast Fourier transformation (FFT) processing based on SDR methodology. It adopts application specific instruction-set (ASIP) and single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. Moreover, a novel 3-dimension multi-bank memory is proposed for parallel conflict-free accesses. The overall throughput and power-efficiency are greatly enhanced by parallel and streamline processing. A test chip supporting 64~2048-point FFT is setup for experiment. Logic synthesis reveals a maximum clock frequency of 500MHz and an area of 0.49 mm2 for the processor's logic using a low power 45-nm technology, and the dynamic power estimation is about 96.6mW. Compared with previous works, our FFT ASIP achieves a higher energy-efficiency with relative low area cost.

This paper presents a programmable and high-efficient application specific instruction-set processor (ASIP) for fast Fourier transformation (FFT) processing based on software defined radio (SDR) methodology. It adopts single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. The proposed ASIP features eight parallel radix-2 butterfly computations with fixed vector data shuffling pattern. In addition, a flexible vector address generation unit is proposed to support inner-and inter-group addressing mode. Experiment results show that the proposed FFT ASIP is much more flexible than previous works and outperforms state-of-the-art FFT ASIP architectures in term of energy-efficiency.

While unmanned aerial vehicle (UAV) is in the mission, the acquired big data information needs to communicate in real-time with the base. Consequently, how to achieve a high-speed and high-quality data transmission via the limited bandwidth and frequency spectrum resource has currently become a hot researching topic in the field of wireless communication and aeronautical telemetry. Aiming at these problems, in this paper, we present a kind of optimization scheme of multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) sphere equalization technology for UAV wireless image transmission data link system, which combines MIMO technology with OFDM technology, thus to increase the spectrum utilization rate and to improve the system performance while resisting to the multipath effect. What’s more, by means of carrying out the collaborative optimization on the original sphere equalization technology (OSET), and by the introduction of the support of the configurable parameters, the system computational complexity is significantly reduced, the detection efficiency as well as the adaptability to complex environment is also improved. Simulation experiment results demonstrate that our method has an approximately optimal bit error rate (BER) performance, a high bandwidth efficiency, a good robustness, a fast convergence rate, and the comprehensive performance is greatly improved than OSET. Furthermore, our method also has a very important reference significance and application value to the development of the equalization technologies of the wireless image transmission data link system based on the UAV platform in our country, as well as to the researches in domestic and foreign related fields.

The technology for multiple-input multiple-output (MIMO) detection is a kind of key enabling technology in high-rate wireless communication, whose performance directly affects the data throughput of the whole system. How to improve the MIMO detection technology, so as to increase the detecting rate and reliability, as well as to lower the bit error rate (BER) has become a hot topic in the field of wireless digital communication. Since the original sphere decoding algorithm (OSDA) has a relatively high computational complexity and a relatively long decoding time, in this paper, we present a new technology for MIMO detection: the μ quantum genetic sphere decoding algorithm (μQGSDA), which combines the super-parallelism of μ quantum computing with the global superiority of genetic algorithm (GA), and can be summarized as a multi-dimensional search for a single-dimensional search, thus to avoid a large number of complex matrix operations, as well as to improve the detection efficiency. Simulation experiment results demonstrate that our method has some advantages of good robustness, search capability and convergence rate. What’s more, the detection performance of μQGSDA has been greatly improved than OSDA.

In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the precision of which is improved to 14th. Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4 us.

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communication domain specific processor, and then proposes a novel processor architecture for the next generation wireless communication named GAEA using this design flow. GAEA is a shared memory multi-core SoC based on Software Controlled Time Division Multiplexing Bus, with which programmers can easily explore memory-level parallelism of applications by proper instructions and scheduling algorithms. MPE, which is the kernel component of GAEA, adopts hybrid parallel processing scheme to explore instruction-level and data-level parallelism. The pipeline and instruction set of GAEA are also optimized for the next generation wireless communication systems. The evaluation and implementation results show that GAEA architecture is suitable for the next generation wireless communication systems.

Software defined radio(SDR) has won much interest for being considered to be in line with the trend of wireless communication development.Now the digital signal processor(DSP) is the bottleneck of software defined radio.The advantages and disadvantages of diverse architecture of software defined radio digital signal processor are summarized,and then the trends of software defined radio digital signal processor are discussed.