Atrial fibrillation (AF) is the most common arrhythmia encountered in clinical practice. Management of AF and stroke prevention remains inadequate in Malaysia.

This work focuses on the development of Integrated Passive Devices (IPD) from electrical design, modeling and simulation till final fabrication and device technology qualification stage. Passivation layer of Polyimide (PI) type was used as inter-metal dielectric materials together with semi-additive copper plated redistribution layer (RDL) as conductive material that carries signal traces through the devices. It also applies multilayer thin film technology used in Wafer-level Packaging (WLP) processes. The thin film setup was designed at 6-layers, which comprises three Polyimide layers and three RDL. Passive devices are designed for Radio Frequency Integrated Circuit (RFIC) applications that work mainly at frequencies of 2.4GHz and 5GHz. For IPD, inductors cover the range of InH and 23nH, and capacitors are within range of 0.03pF to 2.5pF. Several coplanar waveguide (CPW) transmission line structures were also included in the test vehicle prototype to characterize the copper RDL quality in transmitting high-frequency signals at Gigahertz range. Substrate material of low resistivity silicon wafers at 25 Ohm.cm was used for these structures which influences the quality factor of coils and capacitors. Integrated inductors and capacitors structures with stack-up of passivation and copper RDL were designed at realistic Wafer-level thin film thickness, which allows robust integration into WLP platform. Structures correlation of high-frequency measurements and simulation showed maximum of 5% deviation at high-frequency bandwidth. Fabricated structures perform well in time-zero failure analysis and reliability test of High Temperature Storage (HTS 500hr).

Wafer level package (WLP) provides the smallest form factor to satisfy multifunctional device requirements along with improved signal integrity for today's latest handheld electronics. WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Three sizes of LCWLP are designed and simulated, prior to assembly and reliability tests. The structural design features electrical, mechanical and thermal simulations of LCWLP with three chip sizes and ball layout. Simulation results show LCWLPs investigated are able to satisfy the functional and reliability requirements. Electrical simulation demonstrates that LCWLP with the same I/O counts but smaller package size, has better functional performance than FCBGA. Mechanical simulation indicates that wafer level warpage of all LCWLPs studied are within acceptable range for wafer level processes. For board level reliability, LCWLPs are expected to pass the thermal cycling test. Furthermore, LCWLPs are small in sizes with very low junction-to-case thermal resistance, able to keep the maximum junction temperature low and cool the chips during operations. Its thermal performance is strongly influenced by the chip size but independent of the Cu RDL density.

WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Previously, simulations were performed to confirm good electrical, mechanical (warpage and thermal cycling) and thermal performances of LCWLP. Here, process development is carried out to fabricate prototype of LCWLP. Several process issues are successfully resolved. Subsequently, LCWLP is qualified under package level reliability tests, including multi-reflow, solder shear/pull tests, pressure cooker test (PCT), and high temperature storage (HTS) test. After package level qualification, effort will be spent on board level tests. Here, board level drop test simulations are conducted for 3 different sizes of LCWLP. They are shown to have reasonable drop test performance, comparable to typical BGAs.

Numerical simulation of micro-bumped flip chips mounted on a TSV interposer is conducted to study the thermal performance of the package. The 3D package, which consists of two chips, each dissipating 4W, is evaluated under various conditions with its thermal resistances θja θjb, θjc and θjma determined according to JEDEC or MIL-STD standard. Instead of building the detailed model, equivalent thermal conductivity model is adopted for anisotropic bump-underfill layers, silicon interposer and the substrates. Effects of design parameters to the waste heat dissipation, such as the density of TSV in the interposer and the presence of mold encapsulation are investigated. In addition, maximum power dissipation of the package is explored. These modeling results are useful for design optimisation, and also to provide thermal design guideline for a reliable, high performance, and cost-effective 3D package.

Analysis of ground plane design effect for Wafer Level Package (WLP) through advance electrical modeling and simulation for chip-package-board signal integrity co-design was carried out. Increase in information transfer rates is greatly limited by bandwidth of communication channel at PCB board receiver due to channel loss, signal cross-talk, and signal distortion which are critical factors affecting signal integrity of channel and high-speed links such as LVDS, SSTL, LVTTL, LVCMOS and PCI-X. In this work, ground plane design approaches of 2 metal-layer WLP were studied to enhance the signal margin of high-speed signals.

In this paper, a comprehensive and integrated package stress model is established for quad flat non-lead package with detailed considerations of effects of moisture diffusion, heat transfer, thermo-mechanical stress, hygro-mechanical stress and vapor pressure induced during reflow. The critical plastic materials, i.e., moldcompound and die attach are characterized for hygroswelling and moisture properties, which are not easily available from material suppliers. The moisture absorption during preconditioning at JEDEC Level 1, and moisture desorption at various high temperatures are characterized. The moisture diffusivity is a few orders higher at reflow temperature than moisture preconditioning temperature. Due to coefficient of moisture expansion mismatch among various materials, hygro-mechanical stress is induced. The concept is analogous to coefficient of thermal expansion mismatch which results in thermo-mechanical stress. Thermal diffusivity is much faster than the moisture diffusivity. During reflow, the internal package reaches uniform temperature within a few seconds. The vapor pressure can be calculated based on the local moisture concentration after preconditioning. Results show that the vapor pressure saturates much faster than the moisture diffusion, and a near uniform vapor pressure is reached in the package. The vapor pressure introduces additional strain of the same order as the thermal strain and hygrostrain to the package. Subsequently, the interfacial fracture mechanics model is applied to study the effect of crack length on die/mold compound and die/die attach delamination.

Through an aggressive product development program which includes experiment and simulation, Amkor has developed the next level of WLCSP (CSP nl ™), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. Failure mechanism of WLCSP under drop test has been established. Depending on type of WLCSP and test board design, three primary failure modes can be observed, i.e. copper (Cu) board trace crack, Cu RDL (redistribution layer) vertical crack and Cu/Under Bump Metallization (UBM) delamination. CSP nl can exhibit distinct failure modes under different test board and/or CSP nl designs, resulting in a vast difference in drop test lifetimes. The primary failure mode is shifted whenever the weakest link is removed through design improvement. This paper will focus on detailed analysis of copper board trace crack under drop test, using an integrated approach of testing, failure analysis, material characterization and modeling. Board design guidelines are formulated to understand the effects of I/O position, board trace routing direction, board trace width, tear drop design, PCB pad size, stack-up thickness, and alloy materials on board trace reliability. Comparison is also made on possible impact on Cu RDL reliability.

In the current work, a test scheme to evaluate solder joint interface fracture toughness using double cantilever beam (DCB) test has been successfully demonstrated. The obtained results, in terms of critical energy release rate, predict the joint failure based on the principle of fracture mechanics. The results can be used as a materials property in the reliability design of various types of solder-ball joined packages. DCB specimens made of 99.9 wt% copper were selected in the current work. Eutectic Sn-37Pb and lead-free Sn-3.5Ag-0.5Cu solders were used to join two pieces of the copper beams with controlled solder thickness. The test record showed steady propagation of the crack along the solder / copper interface, which verifies the viability of such a testing scheme. Interface fracture toughness for as-joined, extensively-reflowed and thermally aged samples has been measured. Both the reflow treatment and the thermal aging lead to degradation of the solder joint fracture resistance. Reflow treatment was more damaging as it induces much faster interface reaction. Fractographic analysis established that the fracture has a mixed micromechanism of dimple and cleavage. The dimples are formed as a result of the separation between the hard intermetallic compound (IMC) particles and the soft solder material, while the cleavage is formed by the brittle split of the IMCs. When the IMC thickness is increased due to extended interface reaction, the proportion of IMC cleavage failure increases, and this was reflected in the decrease of the critical energy release rate.

Moisture diffusion and vapor pressure development analyses are the key to understand the moisture-induced failure mechanisms in electronic packages. In this chapter, theories and applications of moisture diffusion modeling and vapor pressure analysis are reviewed. The unique characteristics of moisture diffusion in multi-material system are described. The commonly used normalization methods to remove interfacial discontinuity are presented, and the details of thermal-moisture analogy and implementations using commercially available finite element software are discussed. The applications of normalization methods to moisture diffusion in a PBGA package are illustrated. Furthermore, moisture diffusion in a reflow process, in which ambient temperature and humidity loading conditions vary with time, is examined. Caution must be made to apply normalization methods to solve desorption problems when saturated moisture concentration is a function of temperature. A direct concentration approach (DCA) is introduced. In the DCA, the moisture concentration is used directly as a basic field variable, which is discontinuous at interfaces. Constraint equations are applied at interfaces to satisfy the interface continuity requirement. The detailed numerical treatment and implementation procedures using the DCA method are presented. “Over-saturation” phenomenon is observed. Over-saturation refers to a situation in which a material continues to absorb more moisture due to the increase of its saturated moisture concentration despite that desorption takes places during soldering reflow. Finally in this chapter, a whole-field vapor pressure model is introduced. This model is based on a multi-scale micromechanics analysis and considers the phase change of moisture. The model links the macroscopic moisture concentration to a moisture state at a microscopic level. Examples are given to show the differences in moisture and whole-field vapor pressure distributions in a package over time at reflow.

Modeling can efficiently investigate the reliability of new packages, saving time, manpower, and cost for conducting actual tests; A good model is useful for short time-to-market. In this paper, only journal and technical magazine papers are reviewed, many of which report modeling analyses of single die and/or stacked die chip-scale packages. They are summarized regarding the methods, design parameters, and/or results. Brief comparisons are provided on similarities and differences of the effects of the common design parameters on solder-joint reliability. The effects of variations in materials, package designs, the number of dies, test conditions, and board geometry can be investigated efficiently by thermal cycling modeling or drop test modeling.

This paper will share current results of Amkor's WLCSP board level reliability testing for both larger package size and smaller pitch. The 6.8mm test vehicle used for the large WLCSP package testing has 196 I/O set on a 400um pitch uniform array. The 300um pitch package has 100 I/O and is 3.8mm on each side. Amongst other design variations, solder alloy and redistribution layer thickness are explored as a means to enhance reliability. In addition to board level reliability testing, processing challenges will be discussed, as well as lower cost processing solutions for standard pitch designs.

A single-camera technique has been developed to evaluate inplane strains and out-of-plane displacement experienced by a printed circuit board assembly under drop impact. The technique essentially employs a high-speed camera to capture images of the deflecting board surface that had been spray painted to produce fine speckles. A code developed by the Experimental Mechanics Laboratory, NUS, was then used to process the series of images during the period of board flexure by speckle correlation to obtain board strains and deflection data. The results show very good correlation with those obtained from strain gauge technique. Furthermore, as the investigation focuses on dynamic impact, the capturing of localized strain fields close to features such as edges of microelectronic packages and screw/constraint locations, as well as, the overall view of the general board warpage/flexure during different loading conditions makes it a superior method compared to the strain gauge technique that provides only localized data. The single-camera DIC technique takes away the hassle of the traditional two-camera setup and reduces cost of inventory especially for very expensive instruments such as high-speed cameras and lenses. The single-camera DIC technique is a non-contact measurement technique that is easy to setup and implement compared to the strain gauge technique that is a contact method. Mounting of multiple gauges on a flexible specimen such as a PCB may also artificially stiffen the specimen which results in inaccurate data. Furthermore, the DIC method which relies on sprayed particles has spatial resolution that is determined by the smallest speckle that can be observed by the camera, whereas for hard-to-reach places or locations with limited flat surfaces, the use of strain gauges may not be feasible. The single-camera DIC technique not only provides applications to qualitative investigation of board or package deformation but also in material characterization (where specim- ens can be tested in tension or shear and the material properties and responses evaluated together with full-field profiles of their cross-sections); and crack studies (to evaluate full-field strain/stress concentration regions close to notches or other geometrical discontinuities).