Protection capability of high holding voltage (HHV) unipolar and dual-direction SCR devices is studied using TLP, long pulse measurements and mixed-mode numerical simulation toward application for on-chip solutions. The effect of the holding voltage reduction with the increase of electro-thermal stress time is discussed from the point of view of the transient latchup risk.

A novel approach for ESD on-chip protection comprising gate controlled NLDMOS-SCR devices and enable drivers is proposed and experimentally validated. The new principle of clamp design allows operation in two automatically differentiated modes. Protection mode features triggering voltage level significantly lower than maximum operation voltage of the protected pin, while in normal mode the triggering voltage is substantially higher. Reliable functionality of the circuit suitable for voltage domains from 14V to 85V is demonstrated.

The main component level study for combined ESD-EOS protection network specific for battery monitoring pin protection is presented. The focus is made on the suitability of the ESD network for EOS and overvoltage protection. Both short TLP and long stress pulse regime experimental results are presented for the simplified version of the network based on stacked avalanche diode and NLDMOS components.

Physical principles for on-chip solutions with combined ESD, EOS and overvoltage protection (OVP) are presented. The proposed main approach is an upgrade of the conventional ESD protection network components, with extra EOS and OVP capability using additional small footprint clamp and device add-ins. An insight on physical electrothermal processes for EOS stress is presented. The methodology of on-chip performance validation using TLP and long pulse measurements is discussed.

A version of dual-direction SCR (DIAC), with control of the holding voltage and turn-on electrical characteristics by layout parameters, is presented. The effect of additional p-emitter region inside the device floating isolation region on the desired device characteristics is studied. By using an n-collector and/or a p-emitter in the blocking junction of the device, the holding voltage and high current capabilities of the device can be optimized to system level requirements. Experimental measurements and comprehensive mixed-mode TCAD simulations are presented for a 20V tolerant system level cell.

An effective approach to obtain optimal desired characteristics of HV dual-direction SCR ESD protection cell in HV power BCD process is presented. Based on experimental results the proposed dual direction system level ESD cell is realized in form of two independently optimized complementary sub-cells with dedicated positive P-DDSCR and negative N-DDSCR high current path.

Degradation of ESD avalanche diodes breakdown voltage (BV) characteristics in electrical overstress (EOS) regimes is observed and studied in BCD process technology. Both walk-in and walk-out effects are studied as a function of device structure parameters. It was shown that, in constant current avalanche stress regime, the level and direction of BV degradation can be controlled by changing the RESURF poly plate. High current breakdown TLP characteristics have been analyzed for the same phenomena

A complementary HV dual-direction SCR design is presented and studied using electro-thermal mixed-mode analysis. Numerical simulation of triggering, conductivity modulation effects, transient operation under HMM pulse and multi-finger current balancing effects is used to understand the operating principles and optimize the new dual-direction protection approach based on complementary P- and N- DDSCR subcells.

System Level ESD and Fault protection co-design approach on high voltage tolerant transceivers is presented. Two-stage protection network is defined for the case of ±65V CANL output stage. Methodology incorporates dual-directional SCR overshoot at triggering, calculation of parameters for the fault protection snubber clamp and internal circuit pulsed SOA limits.

The latchup isolation of sensitive analog domains from noisy power domains is studied in 85V BCD process technology through comparison of conventional Pwell-ring isolation approach and a novel high impedance isolation with N-Epi moat ring. The impact on HV latchup spacing rules is derived for both high side and low side injection using wafer level 100mA latchup injection and victim detection current data

HV latchup co-design flow based on recently developed EDA tools is presented. The three-step flow targets HV latchup co-design of power analog IC’s, enforces latchup rules, and analyzes sensitivity of the design to the injection current. Key strengths of the automated flow are the ability to identify and annotate injection and victim pockets, followed by area optimization through detection current estimation.

Self-protected LDMOS Open Drain circuit level approach presented. Conventional scheme with stand- alone ESD is eliminated and Output device provides ESD current path via circuit- based solution. Overvoltage and RC triggered versions are shown. No performance degradation at normal operation confirmed. Proposed idea validated by simulations and experimental data.

50 Words Abstract – Degradation of ESD avalanche diodes breakdown voltage in BCD process technology as a result of short term (minutes to hours) electrical overstress in avalanche breakdown regime is studied. It is shown, that the magnitude of the breakdown voltage walk-in or walk-out can be adequately predicted by numerical simulation with setup similar Hot Carrier Degradation for charge trapping effect at silicon-oxide interface and is a function of the device structure parameters.

The problem of ESD and EOS protection of power trains with substantial rail ringing is addressed. An overvoltage protection circuit upgrade of conventional HV Active clamps with power-on shutdown is proposed. The custom control of clamping characteristics is achieved by modification with avalanche diodes. The operation is validated by TLP and Hot-plug-in experiments.

Unexpected latchup qualification test failures of HV analog integrated circuit were observed and explained by a new mechanism - injection current upset of internal HV blocks resulting in overload and burnout of LV circuits. A novel verification algorithm is implemented based on analytical model calibrated with latchup test structures data.

Hot-plug -in (HPI) compatibility of HV rail-based ESD protection networks is addressed by establishing express wafer level test method followed by upgrading HV active clamps. The clamp level solution is validated experimentally by cross -comparing the novel HPI I-V characteristics and TLP I-V characteristics of the original and improved HPI tolerant clamps.

A correlation between latchup conditions induced by injection at standard qualification latchup test and by system-level ESD pulsed current is studied. Through comparison of the standard test and TLP regimes the initial insight about latchup prevention layout spacing rules to withstand the ESD pulse injection conditions is obtained. The cases of low and high side HV pocket-to-pocket transient latchup conditions are also compared.

A clamp level solution for ESD, EOS and overvoltage protection of LV CMOS circuits is suggested and experimentally validated. Based on simulation and experimental results the suggested mini clamp design is found to be adequate for 1.8V maximum operating voltage of protected CMOS devices. The solution is achieved by combination of high threshold voltage reference and two versions of the efficient pull-up drivers. With the simple PMOS driver the clamping voltage is achieved in the range 3.7-4.3V under leakage voltage <; 0.1nA. For the clamp with the CMOS latch driver a 2.7-3.3V clamping voltage range under 0.1nA leakage current at 2V was experimentally demonstrated.

A dual injection latchup phenomenon in rail based ESD protection network was studied using wafer level experiments. When the ESD rail is floating, low side injection causes a positive feedback with the high side diode connected to the power supply. Comparison of dual-injection latchup vs. conventional HV low side latchup isolation is presented.

A strong miscorrelation between TLP maximum current to failure and corresponding estimated onwafer-HMM pulse passing level of dual-direction SCR ESD device was studied. For multiple SCR ESD devices in 5-80V voltage range the effect was represented by low HMM passing level due to burnout of the structure Npocket to P-substrate isolation junction. It is shown that the phenomenon is specific to the on-wafer HMM test setup itself and is the result of the direct strong coupling of the wafer to the prober chuck at system ground under inductive impedance of the HMM tool connection to the DUT.