An important cause of inaccuracies in time dependent VF-TLP measurements of transient events are parasitic inductances/capacitances built into the test setup itself. In this paper it is discussed how to provide confidence of an accurate representation of the DUT properties, by means of characterizations of known inductors/capacitors and simulations.

Time-dependent dielectric breakdown (TDDB) of High-K material is investigated comprehensively by TLP. Cumulative stress effects are eliminated by the TDDB power-law. Promising improvements in the ESD design window for pulses at 1ns are quantified including statistical scattering. With CDM waveforms at gates even substantially below 1ns, CDM design may be eased. Precise design limits can be defined.

We demonstrate a design methodology that combines on-wafer Transmission Line Pulse testing and a simulation setup with a behavioral model for the radio frequency integrated circuit (RF IC). Our methodology enables the early assessment of system-level ESD robustness during the design of the RF IC. The residual stress of an RF port is evaluated using different parallel inductors, which act as a protection element. We show that a TLP pulse width of 10 ns is sufficient to estimate the system-level robustness.

A concise 1-D analytical expression is derived for temperature evolution during pulsed heating. A decreasing exponential temperature profile is shown to be a good approximation for such a profile. It is used to estimate of the failure temperature T rail in two amorphous Indium-Gallium-Zinc Oxide (a-IGZO) TFT technologies and to calculate the onset temperature of negative differential resistance (NDR) in Germanium photodiodes.

Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.

Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of the different buffer material. The layout dependency of ESD behaviors in Si substrate TFTs are investigated in order to meet the 1kV HBM ESD requirement. An on-chip ESD protection design with a gate-coupling TFT is proposed.

A tunable PNP-based ESD clamp is designed for a 4.5V power IO in a foundry technology. Using Mixed-Mode TCAD simulations, we show that the clamp's trigger and holding voltage can be easily tuned by simple layout modifications. The fabricated clamp was characterized using an on-wafer TLP system, confirming the tunable V-T1= 13.4-16.8V, with VHOLD slightly above 10V and I-T2>1.2A. Finally, the clamp is combined with an off-chip transient voltage suppressors (TVS) to withstand surge stress on system-level.

High access resistance is the main limiter for implementation of Germanium into NMOS FinFET device. Growing alternative material on the source-drain (SD) area such as SiGe or Si can solve this issue. Grounded gate NMOS (ggNMOS) devices with five different SD stacks are studied w.r.t. ESD failure level and R on . Small series resistance due to low contact and SD resistance results in very low R on , but harms the ESD robustness dramatically. It was found that high contact resistance and SD resistance act as ballasting resistor similar to the effect of silicide block reported for Si technologies. It prevents current crowding and leads to very uniform conduction. This affect was verified by emission microscope (EMMI) analysis.

We utilized femtosecond time-resolved resonant inelastic X-ray scattering and ab initio theory to study the transient electronic structure and the photoinduced molecular dynamics of a model metal carbonyl photocatalyst Fe(CO)5 in ethanol solution. We propose mechanistic explanation for the parallel ultrafast intra-molecular spin crossover and ligation of the Fe(CO)4 which are observed following a charge transfer photoexcitation of Fe(CO)5 as reported in our previous study [Wernet et al., Nature 520, 78 (2015)]. We find that branching of the reaction pathway likely happens in the 1A1 state of Fe(CO)4. A sub-picosecond time constant of the spin crossover from 1B2 to 3B2 is rationalized by the proposed 1B2 → 1A1 → 3B2 mechanism. Ultrafast ligation of the 1B2 Fe(CO)4 state is significantly faster than the spin-forbidden and diffusion limited ligation process occurring from the 3B2 Fe(CO)4 ground state that has been observed in the previous studies. We propose that the ultrafast ligation occurs via 1B2 → 1A1 → 1A′ Fe(CO)4EtOH pathway and the time scale of the 1A1 Fe(CO)4 state ligation is governed by the solute-solvent collision frequency. Our study emphasizes the importance of understanding the interaction of molecular excited states with the surrounding environment to explain the relaxation pathways of photoexcited metal carbonyls in solution.

Carrier and lattice dynamics of laser excited CdTe was studied by time-resolved reflectivity for excitation fluences spanning about three orders of magnitude, from 0.064 to 6.14 mJ cm(-2). At fluences below 1 mJ cm(-2) the transient reflectivity is dominated by the dynamics of hybrid phonon-plasmon modes. At fluences above 1 mJ cm(-2) the time-dependent reflectivity curves show a complex interplay between band-gap renormalization, band filling, carrier dynamics and recombination. A framework that accounts for such complex dynamics is presented and used to model the time-dependent reflectivity data. This model suggests that the excess energy of the laser-excited hot carriers is reduced much more efficiently by emitting hybrid phonon-plasmon modes rather than bare longitudinal optical phonons.

The impact of wafer thinning down to 5 μm Si thickness is assessed in advanced planar and finFET CMOS technologies. Both Bias Temperature Instability (BTI) and Electrostatic Discharge (ESD) reliability are not impacted by the reduction of the substrate thickness.

Thin Film Transistor (TFT) with amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) as channel material are characterized with TLP and HBM testing. The low mobility of the a-IGZO channel results in an ESD robustness of only 0.3 mA/um. This makes ESD protection design in a TFT technology a challenging task.

A Gate-All-Around (GAA) nanowire (NW) device is a candidate for sub-10nm bulk Si CMOS. The impact of the new architecture and its process options on intrinsic ESD performance needs to be studied. The measurement results and TCAD simulations prove that the ESD performance in bulk GAA NW based diodes is maintained in comparison to bulk FinFET diodes.

Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC. The transient interaction of the parasitic SCR with the surrounding off-chip and on-chip circuitry is investigated during positive and negative system-level ESD stress. It is shown, that sufficient on-chip decoupling and an active clamp can improve the TLU robustness of a circuit.

The ESDA working group 5.6 has conducted single site testing to evaluate the repeatability of passfail results when using the setups in the standard practice 5.6 document. A ten times lower standard deviation is obtained in comparison to the 2011 round robin.