PurposeTo fabricate submicrometer thin membrane of silicon nitride and silicon dioxide over an anisotropically etched cavity in (100) silicon.Design/methodology/approachPECVD of silicon dioxide and Silcion nitride layers of compatible thicknesses followed by thermal annealing in nitrogen ambients at 1,000°C for 30 min, leads to stable membrane formation. Anisotropic etching of (100) silicon below the membrane through channels on the sides has been used with controlled cavity dimensions.FindingsLateral front side etching through channels slows down etching rate drastically. The etching mechanism has been discussed with experimental details.Practical limitations/implicationsVacuum sealed cavity membranes can be realised for micro sensor applications.Originality/valueThe process is new and feasible for micro sensor technologies.

A MEMS process is described to control diaphragm thickness with an integrated provision for back to front alignment in the fabrication of a polysilicon piezoresistive pressure sensor. The end point detection for the diaphragm etching is suitably incorporated in the process so that it is also used for the back‐to‐front alignment. The proposed process is cost‐effective and suitable for the batch fabrication of the pressure sensor.

Polysilicon piezoresistors configured in a Wheatstone bridge, have been fabricated over a silicon diaphragm of 25 to 100 microns thickness for pressure sensing in a range of mbar to tens of bar. A suitable integration of the microelectronics steps with the MEMS technology, has been developed for the fabrication of chips in batches. The developed fabrication process is competent to provide nearly 80 chips of 4 × 4 mm2 size on a two inch diameter silicon (100) wafer with polished surfaces.

The development of PC based Rapid Thermal Chemical Vapour Deposition (RTCVD) system for thin film depositions and annealing is reported. The RTCVD system was built, indigenously, using high intensity linear tungsten halogen lamps as heating source. The temperature and simultaneous control of four reactive gases are achieved through a PC. A software has been developed to control and monitor temperature uniformity within ± 2°C with negligible overshoot/undershoot. The system is capable of handling silicon wafer up to 6” diameter. Low pressure CVD capability of the system make it suitable for sequentlial thin films depositions. In this paper, high temperature growth of very thin Si02 film using tetraethylorthosilicate (TEOS) and oxygen is reported.

Supporting metal electrode thickness in power semiconductor devices should be minimum to achieve high current capability, low saturation voltage and good heat dissipation. But small electrode thickness is found to cause bimetallic bowing of silicon-moly electrode sandwich causing high pressure points on the device element, especially in large diameter wafers. An optimum electrode thickness for a typical 250-mu-m thick silicon darlington wafer (dia 33 mm) has been determined. Silicon darlington (100 A, 500 V) wafers having N-doped substrate have been bonded successfully to molybdenum disk electrodes using AgSbPb (97, 1.5, 1.5) solder preforms in a vacuum furnace to achieve very low ohmic series resistance as compared to fusions fabricated with aluminium alloys. Evaluation of voids at the Si-solder and moly-solder interfaces indicated their absence at 875-degrees-C alloying temperature.

Pure aluminum has been utilized as contact material between power darlington silicon wafer (100 A, 500 V) and molybdenum disk as a back side contact for lightly N-doped substrate. Appropriate temperature profile, assembly fixtures, and optimum aluminum thickness has been used during alloying of silicon wafer with moly disk to minimize silicon dissolution so that segregation of silicon at the liquid–solid interface takes place on silicon side and aluminum freezes out towards moly side giving low resistance ohmic contact, low saturation voltage, and low leakage. Metal base disk thickness has been determined optimally with respect to thickness of device wafer to provide minimum bow of fusion. Evaluation of voids at the moly–aluminum and aluminum–silicon interface indicated their absence at 700 °C bonding temperature.