Mixed-signal integrated circuits (ICs) are critical in various electronic systems, requiring precise and cost-effective testing to ensure their functionality under real-world conditions. A significant challenge lies in the post silicon validation phase, where low-temperature performance screening is a complex, time-consuming, and expensive process. Traditional methods require dedicated, extensive testing at cryogenic temperatures, which substantially increases overall time-to-market and manufacturing costs. This article addresses this critical industry need by proposing an artificial intelligence framework to predict the low-temperature performance of mixed-signal ICs using the efficient low-cost few-shot characterization results from normal and high temperature. A convolutional neural network and least-squares support-vector machine (CNN-LSSVM) model helps to improve the estimation accuracy of full-temperature range performance drift. The convolutional neural network (CNN) is leveraged for automated feature extraction from the high-dimensional test data, while the least-squares support-vector machine (LSSVMs) provides a robust regression engine for accurate performance prediction in highly imbalanced dataset. The efficacy of the proposed framework is validated on 2102 and 4634 sets of measured results from two types of mixed-signal chips. The results demonstrate that it achieves an accuracy of 98.86% and 99.48%, allowing for the reliable pruning of redundant low-temperature test steps. This study provides a highly efficient, supervised learning method that significantly reduces test time and cost for the reliability screening of mixed-signal chips.

Artificial neural networks have recently emerged as a promising tool for digital suppression of passive inter-modulation, yet most studies remain restricted to a small number of transceiver chains and do not address realistic multi-channel deployments. This paper proposes a neural PIM suppression framework for multi-carrier and multi-channel transceivers and studies multilayer perceptron (MLP) and Kolmogorov-Arnold network (KAN) architectures within a compact three-layer model. To balance the limited flexibility of standard MLPs with the computational overhead of KANs, we introduce a streamlined KAN design called SKAN by pruning the edge function to keep only the trainable spline basis expansion. We further tailor SKAN to complex-valued baseband signals through an amplitude-phase structure that preserves phase while applying the nonlinear mapping to the amplitude, which improves feature extraction efficiency and reduces inference cost. We validate the proposed approach on a commercial mobile base station equipped with eight transceiver channels under dual carrier operation. Across this setup, SKAN achieves stronger PIM suppression and faster convergence with fewer trainable parameters and fewer floating-point operations than neural baselines, indicating that it is an effective and scalable solution for practical multi-channel PIM mitigation.

March tests require balancing fault coverage (FC) and test length in embedded memory testing. This brief proposes a novel reinforcement-learning (RL)-based framework that learns optimal March tests by exploiting undetected fault statistics. First, we analyze March tests using a scalable state-tuple-based fault analyzer. Then, we formulate March test generation as a problem to maximize expected FC (EFC) under budget limits. By modeling this as a Markov decision process (MDP), we leverage deep Q-learning to find the optimal operation sequences in March tests, with rewards derived from the proposed fault analyzer. Experimental results demonstrate that our framework generates complementary March tests achieving complete residual FC across a broader range of fault models than the existing methods, with generation efficiency significantly improved through fault analysis completing in milliseconds.

Compressed sensing (CS) enables the reconstruction of sparse signals from sub-Nyquist measurements, but its practical performance is often constrained by severe quantization in hardware implementations. In the extreme low-resolution regime, one-bit compressed sensing (1-bit CS) preserves only measurement polarity, achieving highly efficient acquisition at the cost of degraded reconstruction accuracy, especially under noise and sign-flip distortions. To overcome these limitations, this work proposes a Robust Multi-mapping Correction Framework (RMCF), which integrates multi-link feature mapping with adaptive, weight-voting-based consistency correction. By explicitly modeling channel-dependent sign uncertainty and refining reconstruction thresholds through link-weighted iterations, RMCF ensures stable recovery under high flip ratios. Compared with representative methods such as BIHT, PDASC, and PBAOP, RMCF demonstrates improved robustness to sign flips and faster convergence. Simulation and hardware-level results verify its advantages in reconstruction accuracy, noise resilience, and computational efficiency, highlighting its suitability for hardware-constrained 1-bit CS systems.

Mixed-signal chips, serving as critical interfaces between analog and digital domains, are playing an increasingly important role in modern electronic systems. To accelerate manufacturing tests, adaptive testing has emerged as a promising approach that dynamically adjusts the test sequence, prunes redundant items, and detects defects at minimal cost. Existing studies predict the performance of devices under test (DUTs) from low-cost test items in current and prior stages with different predictors. However, a systematic analysis for selecting appropriate prediction pairs is still lacking. Consequently, a large number of DUTs are required for training, which increases the overall test time and reduces efficiency. To overcome the limitations, this study introduces a correlation-driven method for test-item selection, enabling accurate DUT classification in adaptive testing. Test items are recategorized into “leader,” “follower,” and “uncorrelated” groups based on their extra information gain cost (EIGC), and a backpropagation neural network (BPNN) regression model is used to predict the performance of the “follower” set. The nondominated sorting genetic algorithm is implemented for threshold setting and test-item categorization, considering both test time cost and accuracy. Experimental validation on a commercial mixed-signal chip demonstrates the effectiveness of the proposed method, achieving a defect escape rate as low as 1% with a 40% reduction in test time.

Jitter decomposition is critical for evaluating signal integrity in high-speed digital communications. Conventional and emerging artificial intelligence-based (AI-based) methods struggle to accurately separate complex jitter components, such as periodic jitter (PJ) and duty cycle distortion (DCD), from deterministic jitter (DJ) and random jitter (RJ). To address this, we propose a dual-input VGG-16 convolutional neural network model, termed dual_VGG16_SE_regressor (DVSR), which leverages synchronized jitter histograms and eye diagrams as complementary inputs to automatically predict DJ, RJ, PJ, and DCD components. Extensive evaluation of the simulated data demonstrates high prediction accuracy, with R2 scores of 0.9903, 0.9856, 0.9849, and 0.9977 for DJ, PJ, RJ, and DCD, respectively. Furthermore, the effectiveness of the model is validated using real-world data collected from a dedicated experimental setup, thereby confirming its practical utility for accurate jitter decomposition in high-speed signal analysis. This approach offers a practical, software-based solution that can achieve high-precision, fine-grained jitter decomposition. Unlike existing methods that require high-bandwidth hardware, our work enables standard or legacy oscilloscopes to perform advanced jitter analysis that was previously only possible with expensive, high-end equipment. This represents a significant advancement in test technology, lowering the barrier to accurate signal integrity diagnostics in high-speed digital communications.

In modern communication, radar, nuclear explosion testing, and other fields, there are many complex signals with transient characteristics, such as multi-channel, broadband, short-duration, and random occurrence. To meet the real-time synchronous testing requirements of these signals, this paper presents a high-speed data acquisition system based on time-interleaved (TI) sampling. It enables real-time synchronous acquisition and fast processing for multi-channel broadband signals. First, a modular-based system design scheme consisting of signal conditioning, digital acquisition, data processing, and system control is proposed. Then, the key techniques for system implementation are thoroughly presented and validated, including broadband low-noise signal conditioning, multi-channel precision synchronization, and integrated correction of parallel mismatch error correction. The system demonstrates a maximum bandwidth of 8.1 GHz, a sampling rate of 40GSPS, and a 12-bit resolution. When an 8 GHz monotonous signal is input, the system ENOB reaches 6.864bits, an enhancement of 2.669bits compared to pre-correction, and the SFDR reaches 45.1424dBc, an enhancement of 15.619dBc. Additionally, following correction, the system's flatness in the DC to 7.5 GHz passband is up to -0.56 dB to 0.17 dB, and inter-channel synchronization precision reaches +/- 5 ps from the DC to 8 GHz passband. The design of this system overcomes the limitations of single-ADC sampling rates and temperature-induced delay variations. Compared with conventional single-ADC solutions, it achieves a fourfold increase in sampling rate. In addition, relative to representative broadband acquisition systems employing similar time-interleaved architectures, it achieves a twofold improvement in inter-channel synchronization accuracy, achieving +/- 5 ps precision across the full DC to 8 GHz bandwidth. These advancements make the system well-suited for distortion-free acquisition of broadband transient signals and high-precision multi-channel measurements, providing a practical and scalable solution for ultra-high-speed system development.

With the advancement of radio frequency integrated circuit (RFIC) technology, neural network-based behavioral modeling of RFICs has become an emerging research focus. However, most existing studies focus on optimizing neural network architectures but rely on training and testing datasets with specific and similar characteristics, which constrains the generalization capability of the resulting models. Moreover, simulation-generated data are widely used, further limiting the models’ ability to capture real-world RFIC behavior. To address this issue, this paper introduces an information-rich, band-limited Gaussian signal as the excitation signal for RFIC feature extraction. The datasets are obtained from real-world measurements rather than simulations, enhancing the generalization performance of the trained models. Considering the limited dynamic range of oscilloscopes in practical measurements, we further propose a novel “Weighted Band-Selective Gaussian” (WBS-Gauss) signal, which effectively expands the dynamic range of the collected datasets. Additionally, we develop a causal regression behavioral modeling framework that is compatible with various neural network architectures. Modeling experiments are conducted on RF amplifiers with high nonlinearity and filters with wide dynamic range. The results demonstrate that the proposed excitation signal and modeling methodology enable the construction of behavioral RFIC models with excellent generalization capabilities.

This article proposes a novel frequency-response mismatch estimation method for time-interleaved analog-to-digital converters (TIADCs) based on the Chirp-Z Transform (CZT). Unlike the traditional Fast Fourier Transform (FFT)-based estimation, which suffers from fixed frequency resolution and spectral leakage, the CZT offers flexible frequency mapping with adjustable start frequency, bandwidth, and resolution. This flexibility enables high-precision spectral analysis at arbitrary frequency points, significantly improving the accuracy and stability of amplitude and phase mismatch estimation, particularly near sub-ADC Nyquist boundaries. Both simulation and hardware experiments validate the proposed approach. Therefore, the CZT can avoid spectral leakage by flexibly adjusting its computation parameters. Simulation results demonstrate that the CZT-based estimation reduces spectral leakage and improves calibration accuracy by ∼7 dB compared with the FFT-based method in spurious-free dynamic range (SFDR). Furthermore, a 4-channel 12.5 GS/s TIADC prototype is used to verify the feasibility of the proposed algorithm, showing a 20 dB enhancement in SFDR after calibration. The results confirm that the proposed CZT-based estimation provides a high-resolution, leakage-free, and computationally efficient solution for precise channel mismatch calibration in broadband TIADC systems.

In integrated circuit testing, the diversity and precision of digital test pattern are critical to ensuring the yield of the device under test (DUT). As the integration level of DUTs continues to increase, the digital test module, as a key component of automatic test equipment (ATE), is facing increasingly stringent requirements in terms of pattern formats, output data rates, and edge precision. In this context, this paper presents a Timing Generator and Formatter. As a core component of digital testing functionality, it supports digital pattern generation at speeds up to 3.2 Gbps and accommodates multiple formats, including Return-to-Zero (RZ), Return-to-One (RO), Surround By Complement (SBC), and others.

With the increasing complexity of Radio Frequency Integrated Circuits (RFIC), the difficulty and cost of testing them have also significantly increased. Effective modeling can reduce testing costs. However, traditional SPICE models are not easy to obtain, and S-parameter testing is expensive and time-consuming. In order to achieve simple and accurate modeling of RF devices, this article takes the RF power amplifier PW210 as an example to explore the application of deep learning methods in RF device modeling. This article proposes a new method for twin modeling of RF devices and matches it with appropriate data processing, sampling, model training, and validation methods for testing and application, demonstrating the feasibility of this method. In addition, this article uses TPE and ENAS methods to search for the structure of the constructed residual network, compares their efficiency and accuracy, and finds a model structure suitable for PW210 RF power amplifier.

Coprime array (CA) has gained significant attention due to its high degrees of freedom (DOFs) and large array aperture. Previous researches have focused on improving coprime arrays, but few studies have successfully combined a large array aperture, low mutual coupling, and high DOFs with the number of array elements. In this paper, we propose a novel semi-symmetrical augmented coprime array (SSACA) that strategically positions sensors by arranging M-subarrays and symmetric N-subarrays. This design reduces redundancy lags, and increases DOFs, continuous DOFs, and array aperture, thereby mitigating mutual coupling effects and improving angular resolution for the direction of arrival (DOA) estimation. We derive closed-form expressions for the DOFs, continuous DOFs, and array aperture of SSACA. Simulation results demonstrate that the proposed SSACA outperforms the existing studies regarding higher DOFs, reduced mutual coupling effects, and lower root mean square error (RMSE) in similar application scenarios, particularly in strong mutual coupling scenarios.

This paper presents a DDR memory testing module based on adaptive vector synthesis methodology for high-speed memory validation. The system integrates an Algorithmic Pattern Generator (ALPG) with Universal Buffer Memory (UBM) architecture, achieving sub-80ps edge adjustment and 4 Gbps output rates across 128 channels through 16 parallel processing units with GTY transceivers. Key innovations include adaptive vector synthesis with seamless ALPG/UBM switching, dual-rate control schemes enabling 200 Mbps to 4 Gbps range adjustment, and fault capture with data compression reducing bandwidth by 33%. Experimental validation demonstrates 31.25 ps edge resolution and successful DDR4 testing with comprehensive fault detection capabilities.

In high-speed acquisition systems, time-interleaving(TI) acquisition technology can effectively improve the sampling rate of the system. However, in practical sampling scenarios, the physical parameters of different sampling channels can't be exactly identical. Therefore, sampling non-uniformity mismatches are inevitable. To calibrate this mismatch, this paper proposes a frequency response mismatch compensation method based on parallel fast fourier transform(FFT). The proposed approach has been evaluated with a high-speed acquisition system with sampling rate of 20 GSPS and bandwidth of 8 GHz. Analysis indicates that compared to conventional calibration methods in the time domain, this mismatch calibration approach based on parallel FFT and frequency-domain filtering significantly enhances processing efficiency and reduces the required hardware multiplier resources by more than 50%.

Analog-to-digital converter circuits represent complex dynamic nonlinear systems, where accurate modeling is essential. This manuscript proposes a deep learning model combining an Autoencoder with a Fully Connected Neural Network (AFC-NN) for modeling the dynamic nonlinear behavior of ADCs. The model leverages discrete-time input and output sequences of the ADC within a supervised learning paradigm, enabling single-step prediction of the output encoding from continuous-discrete time-domain input sequences. The AFC-NN model proposed in the manuscript has the following advantages. Its strong nonlinear fitting capability and inherent time-series memory capacity obviate the requirement for researchers to depend on a priori knowledge (e.g., nonlinear order or memory length). The modeling process utilizes random sequences as test stimuli, enabling accurate prediction of the dynamic response to sinusoidal stimuli with varying frequencies and amplitudes. Experimental validation is conducted using an 8-bit pipeline ADC as the target device. Results demonstrate that the AFC-NN framework achieves excellent fitting performance within the Nyquist bandwidth, with a time-domain sequence prediction Mean Absolute Error (MAE) of less than 0.375 LSB, a signal-to-noise ratio (SNR) error of less than 1 dB, and a spurious-free dynamic range (SFDR) error of approximately 2 dBc.

In high-precision digital signal analysis, jitter decomposition is crucial for signal integrity evaluation. Traditional jitter decomposition methods, including dual-Dirac model, exhibit limitations in analyzing deterministic jitter (DJ) and random jitter (RJ) in high-speed signals, making it difficult to accurately separate complex jitter components including duty cycle distortion (DCD), which causes unequal durations of the effective high and low signal levels and will lead to bit errors in high-speed signals. This paper proposes a CNN-based jitter decomposition method for automatic classification and prediction of RJ, DJ and DCD and validates the effectiveness of jitter decomposition by the CNN model, providing new research insights for jitter analysis in high-speed signals. Experimental results demonstrate that CNN model can effectively learn deterministic features of DCD, with 0.0174 ps mean absolute error and 0.021 ps mean square error between predicted and actual values.

March algorithms are essential for detecting functional memory faults, characterized by their linear complexity and adaptability to emerging technologies. However, the increasing complexity of fault types presents significant challenges to existing fault detection models regarding analytical efficiency and adaptability. This article introduces the test primitive (TP), a unified notation that characterizes March test sequences through a novel methodology that decouples fault detection operations from sensitization states. The proposed TP achieves platform independence and seamless integration of fault models, supported by rigorous theoretical proofs. These proofs establish the fundamental properties of the TP in terms of completeness, uniqueness, and conciseness, providing a theoretical foundation that ensures the decoupling method reduces the computational complexity of March algorithm analysis to $O(1)$ . This reduction is analogous to Karnaugh map simplification in digital logic while enabling millisecond-level automated analysis. Experimental results demonstrate that the proposed method significantly enhances both analyzable fault coverage (FC) and detection accuracy, thereby addressing critical limitations of existing fault detection models.

Hexaconazole (Hex) is a common insecticide for fruits and vegetables, but because it is not biodegradable, it can leave behind long-term environmental residues and enter the human body, where it can harm the kidneys and liver. The conventional approach to Hex determination has numerous drawbacks, including low sensitivity and intricate operation. In order to address these issues, the study created PDA@DA-TiO2 using a molecular printing process, dopamine as the polymer monomer, titanium dioxide as the carrier, ammonium persulfate as the initiator, and Hex as the template molecule. PDA@DA-TiO2 was then coated on a quartz crystal microbalance (QCM) using the spin-coating method, and a new portable, machine learning-assisted smart sensor platform (PDA@DA-TiO2-QCM sensor, PDTQ) for the extremely sensitive and focused detection of Hex. The adsorption capacity of PDA@DA-TiO2 (MIPs) for Hex was 2.14 times greater than that of the control PDA@DA-TiO2 (NIPs). Molecular dynamics simulations further uncovered the molecularly imprinted layer's unique adsorption mechanism and recognition locations. The PDTQ demonstrated a strong linear response for Hex in the concentration range of 0.0025-1 mu g/mL, with a detection limit of 0.194 ng/mL. Additionally, a WeChat mini-program was created using the machine learning and deep learning isolated forest algorithm for the temporal in-situ administration of Hex. The findings of the detection were displayed. In real sample testing, the PDTQ demonstrated good recoveries (82.42 %-119.9 %), indicating its potential for quick and precise pesticide residue detection. This study offers a practical and effective way to create a quick-response, user-friendly, low-cost and portable pesticide residue detection platform.

This study presents an efficient method for detecting oxytetracycline, which is critical in environmental monitoring and food safety. A highly sensitive detection platform was developed by combining molecularly imprinted polymers (MIPs) with silica as a carrier, modified with deep eutectic solvents (DES), and a quartz crystal microbalance (QCM) sensor. The MIPs were specifically designed to target oxytetracycline hydrochloride, using SiO2 as the carrier, DES as the functional monomer, N, N-methylenebisacrylamide as the crosslinker, and ammonium persulfate as the initiator. The MIPs exhibited an adsorption capacity of 27.23 mg/g for oxytetracycline hydrochloride. After modification of the MIPs onto a gold electrode surface, a QCM-based sensor platform was constructed. The sensor demonstrated an exceptionally low detection limit of 0.019 ng/mL for oxytetracycline and exhibited excellent sensitivity in tap water. Furthermore, the sensor maintained over 90% detection performance after two weeks of room-temperature storage, indicating its stability. This method provides a rapid, highly sensitive approach for oxytetracycline detection, with potential for future improvements and widespread application in antibiotic testing.

Traditional radio frequency (RF) measurement instruments include the signal generator (SG), spectrum analyzer (SA), and vector network analyzer (VNA). The instrument has the shortcomings of single function and fixed indicators, i.e., it is highly specialized and cannot expand the indicators through software settings. In this paper, a novel measurement system is proposed based on the idea of reconfigurability. This system can switch between SG, SA, and VNA, with the multi-channel direct-conversion transceiver as the hardware core. Compared with traditional instruments, the flexibility and versatility of the system are improved. Meanwhile, the system can expand the instantaneous bandwidth (IBW) indicator to meet broadband test tasks. Additionally, an estimation method for in-phase quadrature (IQ) imbalance is proposed to suppress image interference in the system. The estimation process does not require the assistance of external instruments, and the complexity of the estimation method is low because it avoids complex operations such as iteration. The results show that the system can realize the switching of three functions and the expansion of IBW. The image interference caused by IQ imbalance in the system is suppressed, and the interference rejection ratio can reach up to 80 dB.