Thermal estimation and optimization present a significant challenge in the design of three-dimensional integrated circuits (3D-IC). However, dynamic thermal profiles derived from realistic working scenarios have been neglected during the floorplanning stage so far. Ignoring such time-varying thermal behaviors may lead to suboptimal floorplans, as static or time-averaged thermal models fail to capture the temporal evolution of block-level power distributions under realistic workloads. This paper proposes a power trace-driven floorplanning methodology for 3D-IC that incorporates real functional vectors. First, dynamic power traces are generated through gate-level simulation and vector-based power analysis using functional testbenches. Then, a computationally efficient thermal model based on block-level Green’s functions is proposed to enable dynamic thermal profiling over long power traces. Finally, a thermal dispersion-based perturbation is integrated into the floorplanning process to minimize the peak temperature. Experimental results demonstrate that the proposed floorplanning method effectively reduces the maximum temperature and total wirelength, while maintaining efficient runtime under long dynamic power traces.
Data movement, not computation, dominates the performance and energy cost of data-intensive workloads, from high-performance systems to resource-constrained edge devices. Processing-near-memory (PNM) offers a promising solution by relocating computation closer to data, but practical adoption requires answering two key questions: how to architect simplified cores that fit the area and power constraints near memory, and how to orchestrate kernel execution across host and PNM cores, all while preserving programmability through existing toolchains. This work addresses both through a quantitative design space exploration grounded in physical design validation. Starting from an open-source RISC-V GPGPU, we design memory-proximate SIMT cores by selectively stripping microarchitectural complexity, including caches, warp scheduling, SIMT width, local memory, and division units, inherently preserving OpenCL compatibility by building upon the GPU baseline. We evaluate 22 core configurations across 7 memory proximity scenarios with 24 benchmarks, measured through RTL simulation and physically implemented with SRAM macros on the ASAP7 7nm Predictive PDK. For orchestration, we develop an offloading framework that determines whether each kernel should execute on the host GPU or the PNM core using hardware performance counters available in the baseline architecture. Our results reveal a key codesign insight: the optimal core architecture changes when orchestration is considered. Analysis based solely on hardware favors removing caches for maximum area savings, but evaluation that accounts for scheduling shows that retaining the instruction cache enables significantly more kernels to benefit from offloading. We further find that warp scheduling remains essential regardless of memory proximity, and that kernel offloading preferences shift with input characteristics, justifying runtime adaptation over static decisions. A width-depth scaling study confirms these trends hold up to 512 threads, approaching the thread capacity of a commercial GPU core.
Power estimation for customized accelerators, especially those derived from high-level programming languages, entails the invocation of a long electronic design automation (EDA) tool chain, thus incurring large timing overhead that hinders early-stage design optimization. To mitigate this problem, in this paper, we propose HIPPO, an architecture-level power modeling framework for field-programmable gate arrays (FPGAs). HIPPO operates directly on C/C++ programs, whose execution is prior to and independent of any EDA tool including the very frontend, high-level synthesis (HLS). During power modeling, HIPPO exploits the intrinsic C/C++ code hierarchies and enables multi-level power estimation that aligns with different code hierarchies. Specifically, HIPPO can be decomposed into (1) a code transformation flow that directly converts a C/C++ program associated with HLS pragmas into hardware-oriented and power-aware control and data flow graph, (2) a hierarchy-preserving power modeling methodology that combines analytical modeling and data-driven learning approaches to effectively orchestrate different code hierarchies, (3) a noise-tolerant dataflow coarsening strategy which ensures modeling robustness by suppressing noise of onboard measurement, and (4) a lightweight cross-domain transfer approach that enables the pre-built power model to generalize to new estimation scenarios. Experimental results demonstrate that HIPPO effectively decomposes power consumption and accurately predicts both dynamic and total power, achieving average errors of 8.89% (dynamic) and 6.31% (total) for different applications. Across three transfer tasks, HIPPO reduces the dynamic power estimation error from 18.66% to 15.33%, from 12.03% to 8.88%, and from 7.62% to 5.85%, corresponding to downstream sampling ratios of 20%, 50%, and 100%, respectively. These results highlight the accuracy, efficiency and generalizability of HIPPO for early-stage power analysis, thereby paving the way for power-efficient high-level architecture exploration.
Modern processors incorporate increasingly complex control logic, making efficient and scalable state-space exploration a long-standing challenge in pre-silicon processor verification. While recent coverage-guided processor fuzzing techniques have shown promise, they still suffer from fundamental limitations that hinder verification efficiency, including execution incompleteness induced by uncontrolled control flows, suboptimal test program scheduling under constrained simulation budgets, and excessive redundant mismatches during differential testing. To address these challenges, we present ConFluxFuzz, a coverage-guided processor fuzzing framework that improves verification efficiency by enhancing execution completeness, accelerating coverage convergence, and reducing mismatch analysis overhead. ConFluxFuzz reconstructs control-flow structure during input program construction to enhance realized execution coverage, and adopts a freshness-decayed priority scheduling strategy that prioritizes test programs based on their sustained coverage effectiveness over time. In addition, it incorporates root-cause-aware mismatch filtering to suppress redundant mismatches and reduce manual analysis overhead. We evaluate ConFluxFuzz on four RISC-V processors and analyze its effectiveness across six coverage metrics. Experimental results show that ConFlux-Fuzz achieves higher coverage, faster coverage convergence, and improved bug detection efficiency compared to state-of-the-art coverage-guided processor fuzzers. Notably, for control register coverage, ConFluxFuzz achieves coverage 13.7× faster than DifuzzRTL, 11.0× faster than ProcessorFuzz, and 5.0× faster than riscv-torture, measured by geometric mean, and discovers six previously unknown bugs in open-source RISC-V processors.
Flow-based microfluidic biochips serve as a prominent platform for automating biochemical experiments. A major design challenge is the control layer, where microvalves are pneumatically actuated through ports linked to external controllers. These ports are highly area-intensive and must be placed at the chip’s periphery to avoid interference from external tubing during microscopic observation. This paper introduces a novel methodology for control-layer routing that connects microvalves to user-defined peripheral boundaries. To support control multiplexing, we develop a dedicated bus-routing scheme that bundles microvalves destined for a common boundary, creating a bus for straightforward multiplexer integration. For other microvalves, we cluster them into groups, each managed by a single control port via a tree-based routing structure to minimize port count before finally routing them to chip boundaries. We formally analyze the inherent trade-off whereby clustering reduces the number of control ports but increases routing congestion. A hierarchical clustering algorithm, governed by a dynamic proximity threshold, navigates this trade-off. Furthermore, a parallel Bayesian Optimization (BO) framework enhances the routing process by determining the optimal routing order. We also propose an area-efficient, fault-tolerant structure for critical control channels to improve reliability against blockage defects. Experimental results confirm that our methodology successfully routes all microvalves to their designated boundaries while supporting multiplexer integration. Compared to state-of-the-art methods, our approach significantly reduces control port usage, decreases total wirelength, accelerates optimization, and enhances reliability.
The primary objective of this work is to develop a compact and hardware-efficient methodology for constructing p-bit-based invertible logic circuits using Hamiltonian-based formulations, enabling scalable arithmetic circuit design and demonstrating their applicability to representative NP-hard optimization problems. This work presents the design of p-circuits using the energy function of logic gates. In particular, a three-input majority gate is presented with four p-bits. A weight and bias transformation technique is proposed to eliminate explicit NOT gates by multiplying the corresponding node entries of the weight and bias matrices by -1, without modifying the Hamiltonian. As an application, a three-input minority gate is implemented utilizing four p-bits only, designed using the proposed majority gate. Furthermore, a novel one-bit adder/subtractor is constructed using only six p-bits. The proposed design achieves a graph density of 0.73, whereas existing designs exhibit graph densities greater than 1. The proposed one-bit adder is extended to perform multi-bit addition. Specifically, a 32-bit addition on a p-circuit utilizes 161 p-bits. A 32-bit multiplier is constructed with the proposed adders with 374 p-bits and requires eight connections per node. Various simulations demonstrate the invertible nature of the proposed multiplier as an integer factorizer and division circuit. Moreover, this article explores solutions to a small set of NP-hard problems, such as the subset sum problem, partition problem, and knapsack problem, using the proposed p-circuits for adders and subtractors. Extensive simulations are performed for a small sample of these problems, and the results are presented.
The widespread adoption of high-resolution displays in edge devices such as cameras, smartphones, and televisions has created a growing demand for real-time, high-fidelity image restoration (IR) under strict resource constraints. Conventional deep neural network (DNN)-based solutions rely heavily on multiply-accumulate (MAC) operations and specialized hardware, making them ill-suited for low-power edge deployment. In contrast, lookup table (LUT)-based methods have recently gained attention for their ability to drastically reduce computation through simple memory access. Nevertheless, existing LUT-based methods have yet to be fully deployed on hardware for fixed-resolution (FR) input-output tasks, including denoising, deblurring, and deblocking. To bridge this gap, we propose EdgeLUT, the first fully parallel and pipelined, configurable LUT-based edge accelerator targeting FR tasks. Built with hardware-software cooptimization, EdgeLUT exploits the inherent efficiency of LUT operations to minimize resource usage while sustaining high throughput without any external memory. Implemented on a Xilinx ZCU102 FPGA, our design achieves up to 4K restoration at 216 FPS with 450 MHz, outperforming state-of-the-art (SOTA) FR DNN accelerators with 84% lower logic resource usage, 62% lower power consumption, and complete elimination of digital signal processing (DSP) units. The architecture provides scalable parallelism, consuming 120–408 BRAMs for 1×–4× configurations, explicitly exposing the resource–performance trade-off. Moreover, EdgeLUT delivers up to 3.9× speedup over prior designs, while maintaining a dynamic power of merely 1.3W, demonstrating its suitability for efficient edge deployment.
Deploying diverse machine learning workloads across hardware targets increasingly relies on multi-level compiler stacks built on infrastructures such as MLIR. Production compilers apply fixed, expert-designed optimization pipelines. Hierarchical progressive lowering makes pass ordering consequential in these stacks. Reordering passes can alter dispatch partitioning and backend routing, which changes the downstream tuning space itself. Substantial workload-dependent performance therefore remains untapped. We first show empirically that performance varies substantially across compilation pipelines, and that no single fixed pipeline generalizes across models and tensor shapes. We then investigate why progressive lowering amplifies phase-ordering effects relative to single-level compilers. Using structural and backend-oriented diagnostics, including dispatch topology, code-generation strategy mix, and instruction proxy metrics, we identify tuning-space regime shifts: discrete changes in downstream compilation structure induced by upstream pass reordering. These findings inform the design of BO3 (Beyond O3), a legality-aware three-stage reinforcement learning framework for automated pass ordering in IREE. BO3 combines backend-configuration screening with policy learning over preprocessing-stage pass sequences. It uses graph-based program observations and dynamic action masking to respect structural legality constraints. Evaluated on 9 workload instances from 7 model families on one pinned x86 CPU core, BO3 discovers workload-specific pass sequences that outperform the default IREE -O3 pipeline, achieving a geometric-mean speedup of 5.66×. On the ablated workload, graph-structured observations improve solution quality and dynamic legality masking improves rollout robustness.
Large language model (LLM) execution on commodity hardware with a single discrete GPU remains challenging because model weights, the KV cache, or both can exceed available VRAM. Existing inference backends either require all weights to fit in GPU memory or stream layer weights across the PCIe bus during execution, incurring repeated data transfers that severely limit decode throughput. We present HELM – Compiler-Guided Heterogeneous Execution for LLMs on Memory-Constrained Systems. HELM partitions model layers across CPU and GPU at compile time. HELM uses hardware-calibrated roofline models to search over all feasible contiguous layer-to-device assignments and to select the partition that minimizes per-token decode latency. The plan is compiled into static per-device execution graphs. This eliminates per-token weight movement and reduces cross-device traffic to a single activation transfer per decode step. HELM further includes a paged KV-cache manager that offloads inactive cache pages to CPU memory and an asynchronous streaming-attention kernel. Together they extend the usable context window well beyond GPU VRAM capacity. We compare HELM against vLLM, Hugging Face Accelerate, and DeepSpeed ZeRO-Inference on models ranging from 4B to 32B parameters. In memory-constrained systems where existing backends fail with out-of-memory (OOM) errors, HELM sustains inference by partitioning layers across devices. Where competing backends remain feasible, HELM achieves up to 10.4× higher decode throughput, with a geometric-mean speedup of 6.2× over the strongest feasible baseline, when weights exceed VRAM, while extending the maximum output length by up to 256× (geometric mean 5.9× on feasible Qwen3 family). HELM is available at https://github.com/MPSLab-ASU/HELM.
Carrier–phonon interactions and their associated energy balance models significantly increase the computational cost in the simulations of high-frequency AlGaN/GaN devices, while conventional h- and p-adaptive strategies are ineffective for reducing the number of degrees of freedom in semiconductor simulations, thereby limiting high-fidelity modeling and design optimization of RF chiplets. This paper proposes a region-adaptive energy transport strategy that dynamically deactivates the energy balance equations in near-thermal-equilibrium cold regions of AlGaN/GaN devices, enabling adaptive control of the system degrees of freedom and reducing the overall computational burden. By constructing consistent numerical interface conditionsin the developed algorithm, stable coupling between cold and hot regions with deactivated and activated energy balance models is achieved, where the accuracy of physical field distributions and terminal current are preserved. Numerical results demonstrate that our algorithm can reduce computational cost and memory consumption significantly. For a planar p-gate AlGaN/GaN HEMT, it maintains engineering-level accuracy and achieve a 46.79% cost reduction with terminal current errors of order 10-5. While for a multi-finger AlGaN/GaN Fin-HEMT, the weak parallel efficiency is as high as 82.0%. Further, this research is readily extendable to the other high-frequency semiconductor devices for RF chiplet integration.
Large language models (LLMs) have achieved remarkable performance across a wide range of natural language processing tasks, yet their growing parameter counts and memory demands pose substantial challenges to efficient deployment. Block floating-point (BFP) quantization has emerged as a compelling solution, offering enhanced numerical precision over integer formats while reducing memory overhead via shared exponent encoding. However, a critical yet overlooked source of precision degradation originates from excessive mantissa right-shifting during shared exponent alignment, particularly under low-bitwidth settings. In this work, we propose Dual-Stage Mantissa Shifting (DSMS), a precision-enhancing BFP quantization framework that selectively decomposes the mantissa right-shifting process into two stages: shift encoding and post-multiplication (Post-M) alignment. In the shift encoding stage, small shifts are applied immediately, whereas large shifts are partially deferred to preserve low-order bits. During inference, the deferred shifts are performed after multiplication using the inherently widened bitwidth of multiplier output, thereby mitigating premature truncation and improving inference accuracy. Extensive evaluations show that DSMS improves inference accuracy while maintaining high energy efficiency compared with state-of-the-art baselines.
Specification driven analog repair arises after parasitic extraction, process retargeting, and multi corner closure, where engineers must recover target behavior with a few netlist edits under expensive SPICE evaluation. We study faulty netlists that must be repaired with at most two component level edits and a fixed simulation budget. SpiceDiff Agent couples a patch DSL with topology based connectivity pruning, LLM guided slot ranking, deterministic value enumeration, two-slot lookahead, swap refine, and SPICE verification. On SpiceDiffBench, a 275 task benchmark from eleven circuit templates, it solves all tasks with 30.63 simulations on average, versus 91.48 for filter enabled beam search. Additional ablations isolate the LLM selector, swap refine, lookahead, grid sensitivity, RL/BO baselines, a larger edit pilot, and power/transfer scenarios. The results support a bounded analog ECO style repair claim: topology aware pruning and simulation-grounded planning reduce wasted simulations, while grid co-design, hierarchy, connected decoys, and layout/PPA closure remain open limits.
Replica placement is critical for the performance and reliability of distributed onboard file systems in Low Earth Orbit (LEO) satellite networks. However, inter-satellite networks are highly dynamic due to time-varying topology, intermittent connectivity, and stochastic link failures, which may render file replicas temporarily unreachable during service execution. This leads to a fundamental challenge in jointly ensuring service feasibility, access latency, and replica overhead under unstable network conditions. To address this issue, we study a file-level replica placement problem over a time window and formulate it as a hierarchically constrained optimization problem, where service feasibility is the primary constraint and latency and replica cost are secondary objectives with strict priority ordering. Based on this formulation, we propose ϵ-STAR, an ϵ-relaxed spatiotemporal replica placement algorithm for dynamic intersatellite networks. ϵ-STAR adopts a three-phase design, consisting of full-coverage-first construction, latency-gain optimization, and ϵ-relaxed replica pruning, which together provide a structured approximation to the underlying constrained optimization problem. Extensive experiments under dynamic topology and random link failures show that ϵ-STAR consistently achieves full service coverage while maintaining low access latency and bounded replica overhead, with efficient online execution. Results further demonstrate favorable trade-offs compared with state-of-the-art baselines, indicating its effectiveness for adaptive replica placement in LEO onboard storage systems.
The rise of 3D-ICs, chiplets, and Gate-All-Around architectures demands efficient physical verification of complex inter-layer alignments. Existing multi-layer pattern matching methodologies frequently encounter performance bottlenecks. These limitations primarily arise from the non-negligible overhead of iterative spatial queries and the computational intensity of topological graph construction. Inspired by the Generalized Hough Transform, this work proposes an efficient multi-layer pattern matching framework that utilizes corners as atomic primitives to construct robust geometric signatures. To handle dense layouts with highly repetitive polygon features, a hierarchical filter is introduced with a direct-address hash table. This mechanism significantly accelerates candidate anchor accumulation and prevents performance degradation in large-scale layers. The framework also supports fuzzy matching through selected-corner voting and subsequent verification. Experimental results on large layouts demonstrate the framework's exceptional efficiency in complex multi-layer scenarios. Furthermore, the proposed method achieves 2.4× and 2.3× speedups in single-threaded and 8-thread executions over state-of-the-art approaches on single-layer benchmarks, and an average 28× speedup over the industrial tool Calibre on multi-layer benchmarks. The framework exhibits near-linear time complexity and superior scalability for advanced technology nodes.
Machine learning (ML)-based compact models offer significant advantages in device modeling due to their rapid development cycles and reduced reliance on prior physical knowledge. However, their deployment in industry-standard circuit simulators is hindered by unresolved issues regarding physical consistency, numerical stability, and non-compliant Verilog-A implementation. This paper presents NeuralCM-QA1, an automatic quality-assurance framework specifically designed for ML-based compact models. By integrating OpenVAF, NeuralCM-QA automates model compilation and syntax checking. It performs comprehensive physics-based validation, including Gummel symmetry tests, DC/AC characterization, specification extraction, energy conservation checks, and physical consistency examinations. Furthermore, NeuralCM-QA validates circuit-level convergence using a suite of benchmarks, including inverters, operational transconductance amplifiers, ring oscillators, and six-transistor static random access memory, while providing runtime-aware reporting via a JSON-based configuration. Evaluations using four ML-based compact models trained on a shared BSIM4 dataset demonstrate that NeuralCM-QA reliably distinguishes between models with physical inconsistencies or convergence issues and those suitable for deployment in industrial design flows. A TCAD-trained 5-nm GAAFET case further demonstrates that NeuralCM-QA is not limited to BSIM4-generated ground truth.
Active-matrix digital microfluidics (AM-DMF) integrates semiconductor-derived electrode arrays to enable scalable, high-throughput manipulation of thousands of micrometre-scale droplets. However, existing design automation flows rely on synthesis invocations that require a stable protocol graph and a fixed resource context. Even uncertainty-aware methods typically synthesize static DAG-like fragments after runtime decisions are made. This assumption becomes limiting on highly parallel AM-DMF platforms, where multiple runtime-activated basic blocks may overlap in time, share chip resources. To address this, we propose a two-layer decoupled synthesis framework that maintains a runtime dynamic DAG and separates operation scheduling/placement from droplet routing. The high-level Scheduler/Placer incrementally incorporates newly activated block DAGs and allocates operation locations without pre-computing droplet routes, while the low-level Router computes droplet movements just-in-time under changing blockages, emerging routing tasks, and movement failures. At the framework level, we evaluate two protocol classes under representative realized execution paths and report path-specific makespan (execution cycles), comparing with a sequential batch synthesis baseline. Direct comparison with Puddle’s public implementation further shows that it completes only a limited subset of small representative instances in our setting; within those completed cases, the proposed framework achieves lower execution cycles. Across the evaluated settings, the proposed framework shows generally lower execution cycles than the baseline, with gains depending on path realization and chip scale. At the routing level, the proposed router achieves up to 14× throughput improvement over a modified A*-based baseline, while maintaining decision time below 15 ms on 300×300 chips with up to 400 concurrent droplets. We validate the framework on a physical 128 × 128 AM-DMF platform.
Edge-AI inference on IoT and embedded platforms must satisfy real-time latency under strict energy and cost constraints. Processing-in-Memory (PIM) reduces data movement, but volatile-memory PIM suffers from high standby energy, and NVM-based hybrid PIMs often rely on fixed data placement under dynamic inference demand. This paper presents HH-PIM, a heterogeneous–hybrid PIM architecture with high-performance (HP) and low-power (LP) clusters, each integrating MRAM–SRAM hybrid banks. HH-PIM enables demand-aware weight placement across HP/LP × MRAM/SRAM regions, using SRAM under peak load for latency and MRAM-backed retention with power gating during low-demand intervals. We formulate time-sliced inference as an energy-minimizing weight-placement problem and solve it using dynamic programming, with energy-minimizing placement states precomputed in a look-up table for the formulated discrete placement problem. An energy-aware scalability analysis further captures the convex trade-off between execution-time reduction and logic/idle-power overhead, guiding energy-optimal module-count selection under real-time constraints. RTL implementation with RISC-V–based processor integration shows that HH-PIM achieves up to 86.23% (59.87% on average) energy savings over a volatile-memory PIM baseline across three TinyML CNN workloads and six dynamic scenarios, validating the predicted energy–scalability trend.
Simple Power Analysis (SPA) remains a practical threat to public-key cryptographic implementations, as distinguishable power-consumption patterns may reveal secret keys from a single trace. At CHES 2024, SPA-GPT was proposed as a reinforcement-learning-based method for automated trace segmentation using only the key length. However, its high computational cost can delay post-acquisition single-trace SPA analysis, especially for long traces of public-key cryptographic operations, where segmentation may take tens of minutes. In this paper, we present an efficient automated SPA analysis framework that accelerates trace segmentation while preserving key-recovery accuracy. The framework first applies Fast Fourier Transform (FFT)-based frequency-domain downsampling to obtain a compact trace representation for fast boundary search. Candidate boundaries are located in the compressed domain and then mapped back to the original trace for local refinement, reducing segmentation overhead while preserving the leakage information required for classification and key recovery. In addition, optimizing the reward computation in SPA-GPT and introducing partial pretraining reduce redundant distance calculations and repeated training overhead in reinforcement-learning-based segmentation. Experimental results show that, on five public SPA datasets and one independently collected ECC trace dataset, the proposed method reduces segmentation runtime by 57.07% to 82.09% while maintaining comparable key-recovery accuracy, and achieves up to 100% key-recovery success on applicable datasets.
Chip aging can introduce defects that occur during in-field operation and affect the correct functional operation of the chip. A defect whose presence can affect the correct functional operation is referred to as functionally possible. Functionally possible defects are detected by tests for functionally possible faults (faults whose presence can affect the correct functional operation). It was recently suggested that tests for functionally possible faults with higher susceptibilities to aging should be applied first and more often during in-field test application. The ranking of the faults was based on the functional switching activities at their sites. This article is based on the observation that conventional scan-based test cubes for target faults can also be classified as functionally possible if they can occur during functional operation. Moreover, scan-based test cubes can be ranked based on their likelihood of appearance during functional operation such that a higher ranked cube detects higher ranked faults. To address defects that may appear with aging, the article develops a test generation procedure based on test cube merging that prefers functionally possible test cubes with higher ranks, and places them earlier in the test set. Experimental results for benchmark circuits in an academic simulation environment demonstrate that the procedure includes significantly more and higher ranked functionally possible test cubes in the test set (e.g., over 35,000 test cubes for benchmark circuit b22) compared with a procedure that does not prefer functionally possible test cubes (fewer than 15,000 functionally possible test cubes for b22).
