The paper proposes an original single-phase transformerless three-level (S-PT) photovoltaic (PV) inverter in the cascade H bridge (CHB) configuration. The DC-link voltage of the inverter is created by two serial voltage sources with a voltage twice as low as the DC-link voltage. An appropriate VCC DC-link voltage is generated by a two-phase DC-DC boost converter, fed from the string panel output at a level determined by the maximum power point tracking (MPPT) algorithm. Two symmetrical sources with VCC/2 are formed by a divider of two series-connected capacitors of large and the same capacitance. The common mode (CM) voltage of the proposed inverter is constant, and the voltage stresses across all switches, diodes and gate drive circuits are half of the DC-link voltage. The principles of operation of the S-PT inverter, an implementation of a complete gate control system with galvanic isolation for all IGBTs, are also presented. The proposed inverter topologies have been implemented using high-speed IGBTs and simulated in PSPICE, as well as being experimentally validated.

This paper presents a new self-clocked time-to-digital conversion method which is based on a binary successive approximation algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals i.e. hundreds of microseconds. Therefore, it is suitable e.g. for biomedical applications using time-mode signal processing.

This paper presents a new self-clocked time-to-digital conversion method based on a binary successive approximation (SA) algorithm. Its novelty consists in combining fully clockless operation with direct conversion of the measured time interval. The lack of any reference clock makes the presented method potentially predisposed to low-power solutions. Furthermore, its circuit representation is extremely simple, thereby the ability to direct conversion of time intervals is not burdened by a significant amount of components. The method is intended to measure relatively long time intervals, i.e., hundreds of microseconds. Therefore, it is suitable for e.g., biomedical applications using time-mode signal processing.

Transformerless inverters are widely used in different photovoltaic nonisolated ac module applications, mainly in grid-tied photovoltaic (PV) generation systems, due to the benefits of achieving high efficiency over a wide load range, and low cost. Various transformerless inverter topologies have been proposed to meet the safety requirement of low ground leakage currents, such as specified in the VDE-4105 standard and low-output ac-current distortion. Topology modifications of transformerless full bridge inverters are designed to balance and maintain a constant common mode output voltage, thereby eliminating or reducing leakage currents. This article reviews and compares the different methods for limiting leakage currents in known topologies of the full-bridge transformerless inverters, such as: H4, H5, H6, HERIC, and their improvements. The main topologies and strategies used to reduce the leakage current in transformerless schemes are summarized, highlighting advantages and disadvantages and establishing points of comparison with similar topologies. To compare the properties of different medium to high power inverters, PV inverter topologies were implemented using IGBTs and tested with the same components, same simulation parameters in PSPICE to evaluate their performance in terms of energy efficiency and leakage current characteristics. The detailed power stage operating principles, extended PWM modulator, and integrated universal gate driver with galvanic isolation in the transmission path of control signal for all IGBTs of the inverter, as well isolated and floating bias power supply for gate drivers are described.

This paper presents new and original architectures and implementations of two filterless, open-loop digital Class-BD audio amplifiers with constant common mode (CM) output voltage. The first, low-power amplifier consists of four ultrahigh-current EL7158 pin drivers, the OUT pins of which form the H bridge. The drivers are controlled from the extended LBDD PWM modulator and have appropriately set voltage levels on the VL and VH pins. The second proposed amplifier consists of two cooperating H-bridge power stages (HBS) implemented on complementary MOSFET pairs and powered by two different voltages. Both HBSs are driven by four EL7158 pin drivers having appropriately adjusted voltage levels on the VL and VH pins and controlled by an extended LBDD PWM modulator. The hybrid 9 bit DPWM modulator uses a linearized Class-BD double-sided modulation scheme with pre-compensation, enabling the most faithful emulation of natural NBDD PWM and, thus, providing attractive spectral characteristics at the DM output. Basic SPICE simulations and experimental results of the proposed digital Class-BD amplifiers were compared with the conventional digital Class-BD amplifiers. The elimination of CM signals significantly contributes to the reduction in electromagnetic interference (EMI), particularly those produced on the cables connecting the loudspeaker to the HBS terminal. Proposed Class-BD amplifiers with original and new topologies, due to their simple design and easy control (no galvanic isolation of control signals and no floating bias power supplies), which generate no CM voltage and feature excellent DM performance, similar to conventional Class-BD amplifiers, are very attractive solutions for filterless Class-BD amplifiers.

The paper describes a modification of a dual-slope ADC (Analog to Digital Converter) by using oversampling, noise-shaping and digital filtering techniques. Elaborated MATLAB/SIMULINK models were used to verify the proposed solution. The simulation results show the improvement such as 4-bit dual-slope ADC can be used to reach an effective resolution compatible with 10 bits. The physical implementation of the proposed CIC filter was synthesized into FPGA Artix-7 platform.

The basic distribution methods of time and frequency reference signals are satellite and fiber-optic links as well as the usage of packet networks. All these techniques, however, are exposed to failures and interruptions in the delivery of the reference signal. One of the solutions to solve this problem is implement of backup reference sources-the critical issue is switching the basic signal to the spare one, without losing reference phase. Jumps of phase are highly unwanted for almost every group of users of time and frequency reference signal-from scientists, through the energy industry, to operators of telecommunications networks. In the paper the preliminary measurement results of phase shifter module dedicated to compensate phase shift in the time and frequency transfer system was presented. The module use a typical integrated frequency synthesizer to move phase between input and output signals. System parameters were characterised by the phase noise and the phase shift stability.

In the paper the results of simulation and laboratory experiments relating the influence of features and characteristics of low voltage energetic cables existing in Polish grid infrastructure on efficacy of measurement data transmission via power cables. From data transfer perspective any piece of power cable is a transmission line with certain parameters. The impact of that parameters with a special emphasis on heterogeneity of cable paths on possible transmission quality degradation has been studied in the paper.

Data transmission efficacy depends on interference noise within the transmission band. This apply in particular for smart electric meters using powerline as the transmission medium. The results of laboratory tests of receiver originated noise for the most popular in Poland PLC-OSGP protocol are reported in the paper. Experimentally measured frequency responses for the home appliances potentially influencing the PLC transmission quality are also presented.

In the paper an implementation of mobile nodes tracking system based on ZigBee and Wi-Fi wireless networks is presented. On the base of known algorithmic as well as circuit solutions a simple yet universal system, applied in prototype application dedicated for person's localization in museum premises has been developed. Since system utilizes entirely wireless communication, it can be applied in any closed objects. The system has been preliminarily verified in real in-situ environment.

This paper presents new architectures and implementations of original open-loop Class-BD audio amplifiers with balanced Common-Mode output. The output stage of each proposed amplifier includes the typical H-bridge with four MOSFETs and four additional MOSFET switches that balance and keep the Common-Mode output constant. The presented amplifiers employ the extended NBDD PWM or PSC PWM modulation scheme. When the output stage is built only on NMOSFET transistors, gate drivers require a floating power supply, using a self-boost charge pump with capacitive isolation of the control signal. The use of complementary MOSFETs in the output stage greatly simplifies gate control systems. The proposed amplifiers were compared to the typical Class-BD configuration, using the optimal NBDD modulation with respect to audio performance of the Differential-Mode (DM) and Common-Mode (CM) outputs. Basic SPICE simulations and experimental studies have shown that the proposed Class-BD amplifiers have similar audio performance to the prototype with the optimal NBDD modulation scheme, while at the same time having a balanced constant voltage CM output, thus eliminating the main contributor to radiation emission. As a result, the filtering of the DM output signals can be greatly simplified, while the filtering of the CM output signals can be theoretically eliminated. Practically, due to the timing errors added by the gate drivers, spikes are generated at the CM output, which are very easy to filter out by the reduced LC output filter, even at very low L.

The paper reports the problem of synchronizing clocks in the delta codecs systems with variable length of bits. The original synchronization method, valuable in systems dedicated to transmission the bits with variable time duration was projected and experimentally verified. Performed measures and observations have shown elimination of the synchronization lose phenomenon. Stand on the Spartan 3E evaluation modules, a flexible platform for the implementation the transmission system with non-uniform sampling delta codecs was developed.

Adaptive Non-uniform Sampling Delta Modulation (ANS-DM) is one of the waveform coding techniques, where a sampling instant and a quantization step size are adopted. The ANS-DM modulator produces an output binary stream, that caries information about signal and includes necessary information of coder parameters (sampling instant and quantization step). In demodulator this values have to be recovered for proper signal reconstruction. To date, no systematic investigation that considered signal decoding of the delta systems with sampling instant and step size adaptation were extensively analyzed. In the paper the analytical analysis of a parasitic signal oscillations in the reconstructed signal, as a consequence of the recovery synchronization process in ANS-DM demodulator, have been discussed. Drowned conclusions allow improving the quality of received signal transmitted over ANS-DM system in presence of noises in transmission channels.

In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8kHz and clock generator frequency of 90.3MHz allows us to attain SNR of 120dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.

The pa per con sid ers the po ten tial for new dis cov er ies of gas ac cu mu la tions in the Rotliegend Ba sin onthe ba sis of the anal y sis of res er voir and hydrochemical tests and the re sults of res er voir sim u la tions. Sev eralres er voir sim u la tions car ried out in the study area (his tory of pro duc tion and his tory match ing) dem on strate there gional mi gra tion of res er voir wa ters. The in te gra tion of the sim u la tions with math e mat i cal cal cu la tions (incon sis tency with Hubbert’s the ory) and with hydrochemical re sults per mits rec og ni tion of the re gional hy dro dy -nam ics and the po ten tial lo cal iza tion of gas fields. In an analy sis of the cur rent hydro dynamic and hy drochemicalcon di tions of res er voir wa ters in the Rotliegend (Lower Perm ian) strata, at ten tion was fo cused on part of the sed i -men tary Rotliegend Ba sin, lo cated south of the Wolsztyn-Pogorzela High, uti liz ing ma te ri als avail able fromdrill ing and not ing the dif fer ences be tween this area and the north ern sub-ba sin. The cur rent hydrogeologicalcon di tions and the dy nam ics of fluid trans fer in the Rotliegend Ba sin are an ef fect of struc tural re ar range mentdur ing the Lara mide orog eny. The ba sin hypsometry, re sult ing from the Lara mide move ments, be came the de ci -sive fac tor that con trolled the fil tra tion of ground wa ter. The re cent hy dro dy namic char ac ter is tics of mi grat ingres er voir wa ters are re flected in the P-T (fluid pres sure and tem per a ture gra di ent) dis tri bu tion pat tern. Hence, theanal y sis of this dis tri bu tion may re veal re ac tions that have taken place over time. It must be em pha sized thatclus ters of gas fields are lo cated in the zones oc cu pied by stag nant ground wa ter (rNa/rCl<0.75) un der hydro static(or slightly higher) pres sure.