为解决纳米CMOS工艺下单粒子多节点翻转的问题,提出了一种加固存储单元(RH-12T).在Quatro-10T存储单元基础上对电路结构进行改进,使存“0”节点不受高能粒子入射的影响,敏感节点对的数目是晶体管双立互锁(DICE)存储单元的一半.基于敏感节点对分离和SET缩减原理,进行了加固存储单元版图设计.在相同设计方法下,该存储单元的敏感节点间距是DICE存储单元的3倍.抗SEU仿真结果表明,该存储单元具备单节点翻转全加固能力.全物理模型单粒子瞬态仿真结果表明,该存储单元的线性能量转移(LET)翻转阈值为DICE存储单元的2.8倍,能有效缓解单粒子多节点翻转的问题.

3D-TCAD simulations in a 0 .18 μm process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS .The result turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors .The mechanisms and process that affect the charge collection in both PMOS and NMOS of different layout structures are studied .And suggestions are made towards design guidelines and hardening approaches .

The characteristic of the radiation effect of the 0.13 μm partially depleted SOI technology is researched in this paper.First,the sensitive area of the device in single event upset is studied through 3D simulation,and then the devices′ total ionizing dose(TID) effect is analyzed by experiments.The 3D simulation explored the parasitic bipolar effect and the charge collection of the SOI NMOS devices in case of different strike locations,and showed that both the strikes at the body and drain area could cause relatively great charge collection.The simulation on the SEU of SRAM cell also showed that both the body and reverse-biased drain are sensitive areas to SEU.The result of the TID experiments showed that,the OFF bias state is worse than the TG state for the buried oxide in the device of this technology.

The 3D simulation result shows how the heavy ion strike location, the structure (with or without body contact) of the device, and the energy of strike ion affect the parasitic bipolar gain. Short distance between strike location and body contact reduces the charge collection by drain more obviously than that in the case of longer distance. The highlight of the paper lies in the discovery and analysis of charge collection amplification absence in the device with body contact. Although no bipolar amplification is observed macroscopically, there is still parasitic bipolar element turned on for a short time. The short duration of the electron injection from source and the electron collection of the source reduce the charge collection of drain.

In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.