Energy consumption is one of the most significant aspects of large-scale storage systems where multilevel caches are widely used. In a typical hierarchical storage structure, upper-level storage serves as a cache for the lower level, forming a distributed multilevel cache system. In the past two decades, several classic LRU-based multilevel cache policies have been proposed to improve the overall I/O performance of storage systems. However, few power-aware multilevel cache policies focus on the storage devices in the bottom level, which consume more than 27% of the energy of the whole system [1]. To address this problem, we propose a novel power-aware multilevel cache (PAM) policy that can reduce the energy consumption of high-performance and I/O bandwidth storage devices. In our PAM policy, an appropriate number of cold dirty blocks in the upper level cache are identified and selected to flush directly to the storage devices, providing high probability extension of the lifetime of disks in standby mode. To demonstrate the effectiveness of our proposed policy, we conduct several simulations with real-world traces. Compared to existing popular cache schemes such as PA-LRU, PB-LRU, and Demote, PAM reduces power consumption by up to 15% under different I/O workloads, and improves energy efficiency by up to 50.5%.

The traditional dynamic random-access memory (DRAM) storage medium can be integrated on chips via modern emerging 3D-stacking technology to architect a DRAM shared cache in multicore systems. Compared with static random-access memory (SRAM), DRAM is larger but slower. In the existing research, a lot of work has been devoted to improving the workload performance using SRAM and stacked DRAM together in shared cache systems, ranging from SRAM structure improvement to optimizing cache tags and data access. However, little attention has been paid to designing a shared cache scheduling scheme for multiprogrammed workloads with different memory footprints in multicore systems. Motivated by this, we propose a hybrid shared cache scheduling scheme that allows a multicore system to utilize SRAM and 3D-stacked DRAM efficiently, thus achieving better workload performance. This scheduling scheme employs (1) a cache monitor, which is used to collect cache statistics; (2) a cache evaluator, which is used to evaluate the cache information during the process of programs being executed; and (3) a cache switcher, which is used to self-adaptively choose SRAM or DRAM shared cache modules. A cache data migration policy is naturally developed to guarantee that the scheduling scheme works correctly. Extensive experiments are conducted to evaluate the workload performance of our proposed scheme. The experimental results showed that our method can improve the multiprogrammed workload performance by up to 25% compared with state-of-the-art methods (including conventional and DRAM cache systems).

The potential to promote market value by analysing graph-structured data is increasingly attracting businesses from a variety of industries, ranging from Internet companies to traditional enterprises. However, the query over large graphs easily and efficiently is still a critical problem in large scale distributed systems. Many proposed systems have to use low-level programming model, like Pregel, which requires a large amount of code optimization and maintenance work by developers. Although structural recursion has been studied as an efficient high-level programming model for graph transformations, it is not well exploited in practice to accelerate the parallel graph computing. To address the above problem, in this paper, we propose optimizations of structure recursion for distributed graphs to reduce the number of iterations during graph query processing in a distributed system. In order to improve query response time and throughput, subgraph based computation on structure recursive functions are used to replace typical vertex based evaluation approach. Meanwhile, we propose several redundancy rules to reduce graph size in parallel. We verify the performance of our system through evaluation on real datasets. The results show that, compared to the state-of-the-art approach (Tung and Hu (2015) Towards systematic parallelization of graph transformations over pregel, pp. 1-20. Springer), our algorithm achieves speedup over two times on query response time.

With the enormous and increasing user demand, I/O performance is one of the primary considerations to build a data center. Several new technologies in data centers, such as tiered storage [33], prompt the widespread usage of multi-level cache techniques. In these storage systems, the upper level storage typically serves as a cache for the lower level, which forms a distributed multi-level cache system. However, although many excellent multi-level cache algorithms are proposed to improve the I/O performance, they still have potential to be enhanced by investigating the history information of hints [28]. To address this challenge, in this paper, we propose a novel Hint Frequency-based Approach (HFA), to improve the overall multi-level cache performance of storage systems. The main idea of HFA is using hint frequencies (the total number of demotions/promotions by employing demote/promote hints) to efficiently explore the valuable history information of data blocks among multiple levels. HFA can be applied with several popular multi-level cache algorithms, such as Demote, Promote, Hint-K, etc. Simulation results show that, compared to original multi-level cache algorithms such as Demote, Promote and Hint-K, HFA can improve the I/O performance by up to 20% under different I/O workloads.

Graphs play an important role today in managing big data. Supporting declarative graph queries is one of the most crucial parts for efficiently manipulating graph databases. Structural recursion has been studied for graph querying and graph transformations. However, most of the previous studies about graph structural recursion do not exploit in practical the power of parallel computing. The bulk semantics, which is used for parallel evaluation of structural recursion, still impose many constraints that limit the performance of querying in parallel. In this paper, we propose a framework that systematically generates structural recursive functions from high-level declarative graph queries, then the generated functions are evaluated efficiently on our framework on top of the Pregel model. Therefore, the complexity in developing efficient structural recursive functions is relaxed by our solution.

Graphs play an important role today in managing big data, while structural recursion is powerful to process graphs by its flexibility. Designing efficient structural recursive functions to query distributed graphs is still a big challenge because of the performance constraints imposed by the bulk semantics of structural recursion. In this paper, we propose a solution that systematically generates parallel-efficient structural recursive functions from high-level declarative graph queries. Therefore, the complexity in developing efficient structural recursive functions is relaxed by our solution.

Nowadays mobile data traffic is soaring gradually year by year, the total monthly mobile data traffic (includes uplink and downlink) has come to more than 3,500 Petabytes and the growing trend is continuing. Video streaming demand is the significant contributor of cellular network data traffic, it accounted for more than 45% of mobile data traffic, and the occupancy percentage also is increasing. However the online video playing on mobile devices is still limited by battery technology which does not keep up with the development of cellular networks and mobile processor, mobile users may always need to charge the battery avoiding from device shutting down without power. Currently researchers focus on how to decrease mobile power consumption to prolong the battery lifetime and free mobile devices from charging cables. So it is urgent to understand and decrease the mobile power consumption of online video streaming in LTE networks. In this paper, we conduct a series of experiments to make a deep study of video streaming energy performance characteristics. We design some scenarios for collecting useful mobile power performance data and also measure the state-of-the-art video streaming performance and power consumption. We propose a client-side method to save the power consumption of mobile devices while the video streaming service is using. This method allows multiple video segments can be appended to the video player buffer each time. According to our experimental statistics, the mobile device can save up to more than 30% of the total power consumption for network part by using our multi-appending scheme for online video streaming.

Pregel is a programming model proposed by Google to process large graphs. It is inspired by the Bulk Synchronous Parallel model by which the same computation instructions are applied to every vertex in each iteration. However, Pregel is a so-called low-level model for end users, and it requires much effort on writing efficient programs, even to well-known graph algorithms. Similar problems with the MapReduce model have resulted in high-level query frameworks such as Hive or Pig on top of MapReduce. Taking the same philosophy, in this paper, we propose a high-level framework on top of Pregel to allow executing queries and transformations over large graphs. We borrow UnQL, an SQL-like language over graphs, as the interface language for our framework. UnQL queries are then automatically compiled into efficient Pregel programs that can deal with large graphs. Experimental results with real-life graphs such as citation networks, Amazon products and Youtube, show that our framework is efficient and scalable for large graphs.

Nowadays energy consumption is one of the most significant aspects in Internet operations, where multi-level routing is widely used. In a typical hierarchical router cache structure, the upper level storage serves as a cache for the lower level, which forms a distributed multi-level cache system. In the past two decades, several classic LRU-based multi-level cache policies were proposed to improve the overall I/O performance of storage systems. However, few power-aware multi-level cache policies focus on the storage devices in the bottom level, which consume more than 27% energy of the whole system [20]. To address this problem, in this paper, we propose a novel Power-Aware Multi-level cache (PAM) policy, which can reduce the energy consumption of storage devices with both high performance and high I/O bandwidth. In our PAM policy, a proper number of cold dirty blocks in the upper level cache are identified and selected to flush directly to the storage devices, which provides high probability to extend the duration time of data disks with standby status. Thus the energy consumption can be reduced. Simulation results show that, compared to the existing popular cache schemes such as PA-LRU, PB-LRU and Demote, PAM saves the power consumption by up to 15% under different I/O workloads, which improves the energy efficiency by up to 50.5%.