An 8-channel time-to-digital converter (TDC) with high precision and linearity designed for the electromagnetic calorimeter (EMC) in the Super Tau-charm Facility (STCF) is presented. A 3-level quantization structure is employed in the proposed TDC to achieve high time resolution and wide dynamic range simultaneously. A double-edge-triggered counter characterized by the elimination of metastability is used as the first level. The second and third levels are, respectively, implemented with a polyphase clock sampler and a modified Vernier delay loop (VDL) with an automatic reset mechanism. Two low-jitter delay-locked loops (DLLs) with different lengths are utilized to assist in vernier measurement and polyphase clocks are also provided by one of the DLLs. A theoretical analysis with respect to the optimal combination of DLL length and reference clock frequency is presented. The proposed 8-channel TDC was implemented using 180 nm standard CMOS process with 1.8 V power supply. Under a reference clock frequency of 100 MHz, the TDC is realized with a resolution of 41.7 ps and a dynamic range of 2560 ns. According to the results of an experimental evaluation, the best single-shot precision was 46 ps, and good consistency was observed among all channels. The results also establish that the sliding scaled technique improved conversion linearity. In asynchronous measurements, the maximum differential nonlinearity (DNL) and the integral nonlinearity (INL) were less than 0.4 LSB and 0.5 LSB, respectively.

The COFFEE series is a family of HVCMOS pixel sensor prototypes in a 55 nm process, being developed for the Upstream Pixel (UP) tracker of the LHCb Upgrade II. To handle hit rates up to 322.5 Mhits/s/chip, a behavioral-level simulation of the digital readout circuitry was performed using Monte Carlo hit events as input. Simulation results show that the column-drain readout mechanism achieves near-100% efficiency only when the single readout cycle does not exceed 100 ns; longer cycles cause efficiency loss and non-uniformity. For the peripheral readout adapted to the BXID-sharing data format, six 1.28 Gbps output links are sufficient to accommodate the highest hit density, with the two FIFO stages having maximum occupancies of 23 and 6, respectively, thereby determining the required minimum number of output links and on-chip memory depth. These results provide critical guidance for the COFFEE series design. The column-drain readout mechanism was used in COFFEE3 (fabricated in 2025), while the peripheral readout architecture adapted to the BXID-sharing format is implemented in the COFFEE series successors.

Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed using a 55 nm High-Voltage CMOS (HVCMOS) process. The primary objective is to achieve a time resolution of a few nanoseconds under a hit density of up to 100 MHz/cm(2), while maintaining fine spatial resolution (similar to 10 mu m) and reasonable power consumption (<200 mW/cm(2)). Building on the process validation of the COFFEE2 prototype, this work presents the design and preliminary test results of COFFEE3 - a prototype integrating two distinct readout architectures. Architecture 1, tailored for the current triple-well process, adopts NMOS-only in-pixel circuitry and innovative column-level readout to handle high hit densities. The time walk of pixel-level signal is controlled within 10 ns, and the Time of Arrival (TOA) and Time over Threshold (TOT) are measured with a system clock with the period of 25 ns in peripheral circuits. Architecture 2, developed for future possible processes with p-type buried layer isolation, features pixel-level time measurement and storage. A chip-level Time-to-Digital Converter (TDC) is used and the part of Voltage-Controlled Delay Line (VCDL) is copied in each pixel to get a high time resolution. The TOA resolution is estimated to be 4.2 ns and the TOT resolution 8.4 ns. COFFEE3, with a layout size of 3 & times;4 mm(2), was manufactured and has undergone preliminary tests. Charge injection tests for analog circuits, and laser tests for full readout chains, confirm that both architectures operate as expected. Next step work will focus on characterizing key performance such as the timing resolution, radiation hardness, and tracking performance of minimum ionising particles.

The Circular Electron Positron Collider (CEPC) is a next-generation electron-positron collider for precision studies of Higgs, flavor physics and beyond. A key component of its tracking system is the Inner Tracker (ITK) using High Voltage Complementary Metal-Oxide-Semiconductor (HV-CMOS) sensor technology. The CEPC ITK consists of three barrel layers and four pairs of endcap disks, covering a total active area of about 20 m2. The HV-CMOS sensor fabricated with advanced 55 nm process is used to achieve a few-micrometer spatial resolution and a few-nanosecond timing resolution, with a moderate power consumption. The module design is shared between barrel and endcap to facilitate production. The whole system is designed for minimal material budget, with 0.7% X0 per layer in the barrel part. The design has been implemented in CEPC software framework for performance study and future optimization.

DOI information of incident particle is important for PET system. Accurate DOI acquisition requires dedicated front-end electronics capable of precise energy and time measurement. Our group developed a mixed-signal ASIC with ultra-low noise and wide dynamic range for DOI measurement. To evaluate the ASIC effectively, FPGA-based test systems are required. However, conventional test systems often suffer from synchronization issues between energy and time measurements, which can result in data misalignment or loss under high event rates. In this paper, we present an FPGA-based test system specifically designed to support the evaluation of this ASIC. The system adopts a three-stage processing architecture with dual register arrays for parallel acquisition of energy and time data, enabling precise alignment and high-throughput storage. In addition, the system offers high flexibility and supports real-time acquisition, making it well-suited for accurate and efficient performance testing. The system is validated through functional simulations and on-board tests. Results show reliable real-time acquisition, storage, and transmission of energy and time data, with robust performance under high event rates.

The performance of bipolar transistors used in bandgap voltage reference (BGR) can be degraded by strong radiation, which usually appears in high energy physics experiments. This paper presents a radiation tolerant voltage reference circuit based on a commercial standard 180nm CMOS process. MOS transistors operating in the sub-threshold region were used to replace the bipolar transistors (BJTs) to improve radiation tolerance. The post-layout simulation results demonstrate that the output voltage of the proposed voltage reference circuit is 391mV with a temperature coefficient (TC) of 100.538 ppm/degrees C, when the temperature ranges from -40 degrees C to 125 degrees C The voltage Line Sensitivity (LS) is 0.259%/V, and the power supply rejection (PSR) is -90.1 dB @DC and -37 dB @1 MHz. The power consumption is 44.9 mu W at 27., with a die area of 0.0072 mm(2).

The Circular Electron-Positron Collider (CEPC), as the next-generation electron-positron collider, is tasked with advancing not only Higgs physics but also the discovery of new physics. Achieving these goals requires high-precision measurements of particles. Taichu seires, Monolithic Active Pixel Sensor (MAPS), a key component of the vertex detector for CEPC was designed to meet the CEPC's requirements. For the geometry of vertex detector is long barrel with no endcap, and current silicon lacks a complete digitization model, precise estimation of cluster size particularly causing by particle with large incident angle is needed. Testbeam results were conducted at the Beijing Synchrotron Radiation Facility (BSRF) to evaluate cluster size dependence on different incident angles and threshold settings. Experimental results confirmed that cluster size increases with incident angle. Simulations using the Allpix^2 framework replicated experimental trends at small angles but exhibited discrepancies at large angles, suggesting limitations in linear electric field assumptions and sensor thickness approximations. The results from both testbeam and simulations have provided insights into the performance of the TaichuPix chip at large incident angles, offering a crucial foundation for the establishment of a digital model and addressing the estimation of cluster size in the forward region of the long barrel. Furthermore, it offers valuable references for future iterations of TaichuPix, the development of digital models, and the simulation and estimation of the vertex detector's performance.

The escalating demands of High-Energy Physics (HEP) experiments impose significant challenges on pixel readout chips, including growing functional complexity, compressed design cycles, and high fabrication costs. Traditional verification approaches, relying heavily on static stimuli and manual inspection, suffer from insufficient coverage, low automation, and poor reusability, thus failing to guarantee the functional integrity of such complex designs. To address these challenges, this work proposes and implements a reusable verification framework based on the Universal Verification Methodology (UVM), specifically tailored for advanced pixel readout chips. The key contributions of this framework include: (1) a physics-aware stimulus generator for emulating realistic particle-hit events; (2) a generic serial bus configuration component leveraging the Register Abstraction Layer (RAL) to enable high-level automated configuration; and (3) an intelligent scoreboard capable of out-oforder data matching to ensure robust data validation. The framework's effectiveness was validated on a pixel readout chip, where its metric-driven verification (MDV) methodology successfully exercised complex functionalities and corner cases of the design. By adopting a modular architecture, the framework significantly enhances reusability and efficiency, offering a systematic and scalable solution for the verification of similar mixed-signal chips.

Electron–positron colliders operating in the GeV center-of-mass range, or tau-charm energy region, have been proved to enable competitive frontier research due to several unique features. With the progress of high-energy physics in the last two decades, a new-generation Tau-Charm factory, called the Super Tau-Charm Facility (STCF), has been actively promoted by the particle physics community in China. STCF has the potential to address fundamental questions such as the essence of color confinement and the matter–antimatter asymmetry within the next decades. The main design goals of the STCF are a center-of-mass energy ranging from 2 to 7 GeV and a luminosity surpassing 5 × 1034 cm−2 s−1 that is optimized at a center-of-mass energy of 4 GeV, which is approximately 50 times that of the currently operating Tau-Charm factory—BEPCII. The STCF accelerator has two main parts: a double-ring collider with a crab-waist collision scheme and an injector that provides top-up injections for both electron and positron beams. As a typical third-generation electron–positron circular collider, the STCF accelerator faces many challenges in both accelerator physics and technology. In this paper, the conceptual design of the STCF accelerator complex is presented, including the ongoing efforts and plans for technological research and development, as well as the required infrastructure. The STCF project aims to secure support from the Chinese central government for its construction during the 15th Five-Year Plan (2026–2030).

This study presents a low-noise, high-rate front-end readout application-specific integrated circuit (ASIC) designed for the electromagnetic calorimeter (ECAL) of the Super Tau-Charm Facility (STCF). To address the high background-count rate in the STCF ECAL, the temporal features of signals are analyzed node-by-node along the chain of the analog front-end circuit. Then, the system is optimized to mitigate the pile-up effects and elevate the count rate to megahertz levels. First, a charge-sensitive amplifier (CSA) with a fast reset path is developed, enabling quick resetting when the output reaches the maximum amplitude. This prevents the CSA from entering a pulse-dead zone owing to amplifier saturation caused by the pile-up. Second, a high-order shaper with baseline holder circuits is improved to enhance the anti-pile-up capability while maintaining an effective noise-filtering performance. Third, a high-speed peak-detection and hold circuit with an asynchronous first-input-first-output buffer function is proposed to hold and read the piled-up signals of the shaper. The ASIC is designed and manufactured using a standard commercial 1P6M 0.18 m mixed-signal CMOS process with a chip area of 2.4 mm×1.6 mm . The measurement results demonstrate a dynamic range of 4–500 fC with a nonlinearity error below 1.5 % . For periodically distributed input signals, a count rate of 1.5 MHz/Ch is achieved with a peak time of 360 ns, resulting in an equivalent noise charge (ENC) of 2500 e^- . The maximum count rate is 4 MHz/Ch at a peak time of 120 ns. At a peak time of 1.68 s with a 270 pF external capacitance, the minimum ENC is 1966 e^- , and the noise slope is 3.08 e^-/pF . The timing resolution is better than 125 ps at an input charge of 200 fC. The power consumption is 35 mW/Ch.

Unmanned Aerial Vehicle (UAV) sensors play a vital role in maintaining flight safety and stability. However, the increasing frequency and complexity of sensor attacks have emerged as a critical threat to UAV systems. The current lack of robust multi-classification methods for detecting sensor attacks limits the effectiveness and completeness of existing defense strategies. This research addresses these challenges by leveraging machine learning (ML) techniques to classify various sensor attacks using heterogeneous sensor data and control parameters, thereby enhancing UAV system security. In this study, we design and implement multiple sensor attack scenarios targeting gyroscopes, accelerometers, barometers, and GPS. Comprehensive datasets are collected during UAV flight, integrating diverse sensor readings, flight states, and control parameters. By analyzing the characteristics of sensor attacks and their impact on position estimation and attitude control, we identify and extract key features. To optimize the classification model, we employ feature importance analysis, correlation analysis, and ablation experiments, significantly reducing data dimensionality and enhancing model training efficiency. The experimental results demonstrate the proposed ML-based multi-classification model’s superior performance, achieving a detection rate of 89.38%, significantly outperforming traditional single-attack detection methods in terms of generalization capability. Our approach efficiently handles complex multi-sensor attack scenarios. Moreover, deploying the optimized model on UAV firmware enables real-time monitoring and classification, achieving an online detection rate of 74% with a response time of approximately 0.495ms per detection. The model’s lightweight design, requiring only 48KB of storage, makes it ideal for resource-constrained UAV environments. These contributions highlight the potential of our approach to enhance real-time anomaly detection and improve UAV system resilience against diverse sensor attacks.

A 16-channel Time-to-Digital Converter (TDC) with high precision and high linearity for time of flight (ToF) measurement is presented. The 3-level Nutt-based structure is employed in the proposed TDC to achieve high resolution and wide dynamic range simultaneously. A novel vernier measurement structure based on two Delay Locked Loops (DLLs) with different frequencies is proposed in this work, with which 10-ps resolution can be achieved with less jitter accumulation and moderate frequency. The proposed 16-channel TDC is implemented using 180-nm standard CMOS process with 1.8-V power supply. Under the operating clock frequencies of 240-MHz and 280-MHz, the TDC is realized with a resolution of 10.6-ps and a dynamic range of 1066-ns. According to testing results, the best single-shoot precision of 13.7-ps and good consistency among all channels can be observed. In asynchronous measurements, the maximum differential nonlinearity (DNL) and the integral nonlinearity (INL) are less than 0.5-LSB and 1-LSB respectively.

This study conducted Co-60 gamma-ray irradiation experiments on commercial-off-the-shelf (COTS) image sensors, analyzing the quantitative relationship between dark current amplitude distribution characteristics and incident dose. A dark current distribution model was established, and a novel incident dose prediction method based on statistical feature fitting was proposed. Experimental results demonstrate that the prediction errors remain within 15%.

Unmanned Aerial Vehicles (UAVs) are typical real-time embedded systems, which require precise locations for completing flight missions. The Global Navigation Satellite System (GNSS) plays a crucial role in navigation and positioning for UAVs. However, GNSS spoofing attacks pose an increasing threat to GNSS-dependent UAVs. Existing spoofing detection methods primarily rely on simulated data, perception data from multiple UAVs, or various control parameters. This paper proposes SigFeaDet, a signal feature-based GNSS spoofing detection approach for UAVs utilizing machine learning techniques. The core concept revolves around identifying anomalies in signal features arising from differences between authentic and spoofing signals. Key signal features, including Carrier-to-Noise Density Ratio (CN0) and Doppler frequency crucial for GNSS positioning, are employed to discern spoofing signals. Various machine learning algorithms are leveraged to train on GNSS signal data, determining the most effective classifier. TEXBAT GNSS dataset is processed to extract spoofing signal data, and flight experiments are conducted to gather GNSS data, augmenting the authentic GNSS signal dataset. The detection accuracy exceeds 95%. Equal Error Rate (EER) is approximately 5%. We evaluate various impact factors on SigFeaDet to show its robustness, including differences in velocities, altitudes, and experimental locations (10 kilometers apart), and the accuracy consistently surpasses 99%.

The proposed Circular Electron Positron Collider (CEPC) presents several challenges for the vertex detector, including material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix has been developed for the CEPC vertex detector. To evaluate the performance of the TaichuPix-3 prototype, a beam test was conducted at the DESY II TB21 facility. This work presents the analysis results of the offline beam data, including cluster size, spatial resolution, and multiple scattering studies, which indicate the intrinsic resolution of TaichuPix-3 chips is less than 5 mu m and the material budget is measured to be 0.170 +/- 0.018%.

Download This Paper Open PDF in Browser Add Paper to My Library Share: Permalink Using these links will ensure access to this page indefinitely Copy URL Copy DOI

The Circular Electron Positron Collider (CEPC) has been proposed to enable more thorough and precise measurements of the properties of Higgs, W, and Z bosons, as well as to search for new physics. In response to the stringent performance requirements of the vertex detector for the CEPC, a baseline vertex detector prototype was tested and characterized for the first time using a 6GeV electron beam at DESY II Test Beam Line 21. The baseline vertex detector prototype is designed with a cylindrical barrel structure that contains six double-sided detector modules (ladders). Each side of the ladder includes TaichuPix-3 sensors based on Monolithic Active Pixel Sensor (MAPS) technology, a flexible printed circuit, and a carbon fiber support structure. Additionally, the readout electronics and the Data Acquisition system were also examined during this beam test. The performance of the prototype was evaluated using an electron beam that passed through six ladders in a perpendicular direction. The offline data analysis indicates a spatial resolution of about 5 μm, with detection efficiency exceeding 99% and an impact parameter resolution of about 5.1 μm. These promising results from this baseline vertex detector prototype mark a significant step toward realizing the optimal vertex detector for the CEPC.

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix, based on a column drain readout architecture, has been developed to address the need for high spatial resolution. In order to evaluate the performance of the TaichuPix-3 chips, a beam test was carried out at DESY II TB21 in December 2022. Meanwhile, the Data Acquisition (DAQ) for a multi-plane configuration was tested during the beam test. This work presents the characterization of the TaichuPix-3 chips with two different processes, including cluster size, spatial resolution, and detection efficiency. The analysis results indicate the spatial resolution better than 5 µm and the detection efficiency exceeding 99.5 % for TaichuPix-3 chips with the two different processes.

本研究介绍了一款为超级陶粲装置（STCF）电磁量能器（ECAL）而设计的低噪声、高计数率前端读出应用专用集成电路（ASIC）。为了解决 STCF ECAL 的高背景计数率问题，本文分析了模拟前端读出电路信号链中各个节点信号的时间特征，据此对系统进行了优化设计，以减轻堆积效应影响，将计数率提高到了兆赫兹级别。首先，设计了具有快速复位路径的电荷敏感放大器 (CSA)，使其能够在输出达到最大振幅时快速复位，防止CSA因堆积饱和而进入死区。其次，改进设计了带有基线保持电路的高阶滤波成形器，以增强抗堆积能力和噪声滤波性能。最后，提出了一种具有异步先入先出缓冲功能的高速峰值采样和保持电路，用于采样保持和读取滤波成形器输出的信号。该ASIC采用标准商用 1P6M 0.18 μm混合信号 CMOS工艺设计和制造，芯片面积为2.4mm × 1.6mm。测试结果表明，其动态范围为 4-500 fC，非线性误差低于1.5%。对于周期性分布的输入信号，设置达峰时间为360 ns，计数率可达1.5MHz/Ch，等效噪声电荷(ENC)为2500 e-。设置峰值时间为120 ns时，ASIC最大可接收计数率为4MHz/Ch。在峰值时间为1.68 μs且输入端外加270 pF电容时，ENC最小为1966 e-，噪声斜率为3.08 e-/pF。在输入电荷大于200 fC时，时间分辨率优于125 ps。芯片平均功耗为35mW/Ch。