A snapback-free Reverse-Conduction Lateral Insulate Gate Bipolar Transistor with a Hole Extraction Path (HEP LIGBT) is proposed for the first time in this paper. The N-channel HEP LIGBT can conduct with the P-type drift region (P-Drift) and Semi-Insulating Polycrystalline Silicon because an inversion layer of electrons is formed on the P-Drift, which connects the N-channel to the N-type buffer layer. And due to the fact that the generation and quantity of electrons in HEP LIGBT no longer depend on doping concentration, this alleviates the contradictory relationship between the Breakdown Voltage (BV) and on-state voltage drop (Von). Additionally, when HEP LIGBT is turned off, the P+ cathode/P-Well/P-Drift structure creates a hole extraction path in the P-Drift. Therefore, holes in P-Drift under large injection state can be eliminated through extraction rather than recombination. Compared with the Separated Shorted-Anode RC-LIGBT (SSA LIGBT), through TCAD simulation, the Von (1.07V), turn-off time (toff=12.41ns) and turn-off loss (Eoff=0.21mJ/cm2) of HEP LIGBT reduced by 26.8%, 74.4% and 77.1%.
An ultra-broadband CMOS low-noise amplifier (LNA) operating from 6.65 to 32.75 GHz is presented for high-capacity wireless systems. The proposed design incorporates a novel Supplementary Broadband Gain Stage (SBGS) integrated with a gm-boosted common-gate architecture to achieve simultaneously high gain, wider bandwidth, and competitive figure of merit (FoM). The proposed SBGS employs RC feedback, modified Darlington-based transconductance devices operated under power-constrained biasing, and microstrip-line-based inter-stage and output matching networks to suppress high-frequency gain roll-off, enhance gain flatness, and provide wideband impedance matching. The Microstrip Line (MSL) based matching network (MIMN/MOMN) serves a dual role by achieving effective impedance matching while facilitating noise and gain co-optimization. The proposed design reduces the parasitic capacitances while enhancing the equivalent transconductance which results in an LNA with a notably high peak gain of 25.31 dB and low noise figure (NF) of 4.2 dB across a significantly wider frequency band. The design exhibits input and output 1-dB compression point (IP1dB & OP1dB) of −26 dBm and −11.1 dBm respectively, while the input and output third-order intercept point (IIP3and OIP3) are 0 dBm and 15.9 dBm, respectively indicating an adequate linear behaviour with reduced distortion despite the high gain. Statistical analysis and Design of Experiment (DoE) results show the yield to be >97% emphasizing the design robustness against ±5% parametric variations. The design is fabricated using commercial 28 nm CMOS process and occupies die area of 0.42 mm2. With power consumption of only 11.7 mW, the SBGS operates as a power-efficient gain bandwidth boosting technique, while the proposed LNA demonstrates excellent overall performance, achieving a competitive FoM of 22.72.
To meet the demands of 5G millimeter-wave communication systems for on-chip filters with miniaturization, high selectivity, and strong anti-interference capability, this paper proposes a fourth-order phase/electromagnetic hybrid-coupled topology. The electric and magnetic coupling are arranged, producing multiple transmission zeros (TZs). Two balanced bandpass filters (BBPF I and II) centered at 28 GHz are designed, fabricated, and measured. The measured results show that both filters have a compact size of 2.3 × 3.6 mm (0.12 λg2). BBPF I exhibits a 3 dB fractional bandwidth (FBW) of 28%, an insertion loss (IL) of 1.9 dB. By cascading the symmetric resonator, BBPF II mitigates the high-frequency common mode resonance, increasing the 3 dB FBW to 29%, reducing the minimum IL to 1.8 dB, and achieving common mode suppression greater than 14.1 dB in the 16-32 GHz band. BBPF I and II exhibit upper-stopband TZs at 36.9/38.7 GHz and 36.2/38.6 GHz, respectively, demonstrating a compact and high-selectivity balanced-filter solution for 5G millimeter-wave front ends.
This paper presents a digital foreground calibration scheme for high-resolution pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs) to address capacitor mismatch and inter-stage gain error. A 20-bit behavioral model is established, and the search for optimal weight coefficients is formulated as the minimization of the negative signal-to-noise-and-distortion ratio (SNDR). The whale optimization algorithm (WOA) performs global and local search, while a lightweight genetic algorithm (GA) module activates upon stagnation to maintain diversity and escape local optima. A comparator metastability-detection technique extracts and compensates first-stage offset. Simulation results show that the proposed hybrid calibration algorithm improves the ADC’s SNDR from 68.34 dB to 103.89 dB, yielding an enhancement of approximately 35 dB, with repeated trials confirming robust stability. The offset calibration technique extends the tolerable comparator offset range to roughly ±11 mV.
This paper presents a 0.6-V closed-loop ping-pong auto-zero (AZ) amplifier that suppresses offset and flicker (1/f) noise suppression in low-voltage precision amplifier applications. By exploiting the intrinsic PMOS body transconductance through back-gate feedback, the proposed architecture embeds the dynamic offset-cancellation (DOC) loop into the main amplifier core, eliminating the auxiliary input transconductor required in conventional ping-pong AZ implementations. The resulting merged gate/body-transconductance structure reduces active-area and current overhead while preserving continuous-time operation with two alternating AZ channels. Fabricated in a 180-nm CMOS process, the prototype operates from a 0.6-V supply, consumes 5.26 μW, and occupies 0.098 mm2. Measurements show that AZ reduces the 1-Hz input-referred noise from 8.36 to 4.33 μV/√Hz and suppresses the mean input-referred offset to 274 μV, demonstrating reliable offset/noise reduction for low-voltage precision amplifier applications.
Epileptic signals are complex and diverse, and traditional manual detection is time-consuming, labor-intensive, and prone to high error rates. Therefore, there is an urgent need to develop efficient and reliable automatic epilepsy detection technologies. This study proposes a low-power, lightweight epilepsy detection IP design based on Sparse Convolutional Neural Network (SCNN). First, the scheme utilizes oversampling techniques to balance the sample distribution and combines bandpass filters to suppress noise. Second, a lightweight one-dimensional sparse convolutional neural network model is constructed; unstructured pruning is employed to determine the optimal sparsity, and a threshold-based wake-up mechanism is introduced to achieve dynamic power consumption control. Finally, a sparse weight compression storage format is designed to build a highly energy-efficient sparse convolutional neural network hardware architecture. Validated on the CHB-MIT dataset, the epilepsy detection accuracy reached 99.24%. Designed using the TSMC 28nm process, the chip area is 0.595mm2, power consumption is 15.38mW, single-detection latency is 0.343ms, and energy consumption is 5.27μJ/class.
