A new design for high efficiency silicon solar cells with the use of limited p-n junction area and point Al rear contact is proposed. In this work, planar test devices with different emitter area and spacing are fabricated to demonstrate the limited junction area (LIA) design can improve VOC for a well-designed cell structure. Interim lifetime and PL measurements during fabrication confirm lower dark saturation current (I0) and higher implied VOC (iVOC) in the LIA samples with a robust surface passivation scheme. Higher VOC and efficiency are also simulated with Quokka on some LIA devices compared to the full area emitter control sample.

A limited area p-n junction approach can increase the open circuit voltage (Voc) of silicon solar cells when the emitter recombination dominates. A limited area p-n junction silicon solar cell is designed and the effect of reducing emitter areas on the Voc, short circuit current (Jsc) and fill factor (FF) is studied using the 3-D simulator Quokka. This paper compares the modelling result of this approach on structures with different values of emitter recombination. It is concluded that voltage improvement can be achieved when the emitter dominates the total recombination. The result also shows that the current collection and FF can be maintained with an optimized unit cell design. The paper also extends the approach to thin (20μm) solar cells, demonstrating the potential for Voc values up to 770mV when excellent surface passivation is employed.

A limited area p-n junction silicon solar cell is designed and the effect of limited area emitter on the output open circuit voltage (VOC) and efficiency is studied by a 3-D simulator Quokka. The recombination property of emitter, surface and bulk are all extracted from the test structures and this paper reports potential voltage that can be achieved on the limited area junction solar cells by the modelling. The result indicates that this approach will help improve VOC when the emitter area is reduced and the voltage will be more than 700mV. The result also shows that there is an optimum emitter width for the highest efficiency on the limited area junction solar cell.

A method of patterning atomic layer deposition (ALD) deposited aluminium oxide dielectrics (Al2O3) using an inkjet printer is outlined. This method has applications in creating PERC cell type rear contacts. It is simpler, and uses fewer chemicals than immersive etching techniques such as those involved in photolithography, and the patterning does not cause damage to the silicon evident in laser ablation techniques. Holes with varying diameter between 61–159 µm were etched onto a 50 nm thick ALD Al2O3 passivating dielectric at numerous print settings. The relationship between the printing parameters and the feature size of the holes is discussed.

A study of limited area p-n junction silicon solar cells using photoluminescence (PL) is used to demonstrate the pathways to an increase in open circuit voltage (VOC). A high voltage baseline structure is used to ensure that the junction dominates the recombination. Both quasi-steady-state photo-conductance (QSSPC) and PL measurements indicate higher implied voltage on the limited p-n junction area solar cells compared to full area junction cells. This work aims at achieving more than 740 mV VOC on the limited area junction structure, through optimising the passivation layers and comprehensive analysis of voltage losses throughout the structure. Various choices of passivation layers and a new structure design for separating and analysing J0 from each component on the limited area junction solar cell will be presented in this paper.

The practical realization of high efficiency laser-doped semiconductor fingers (SCF) silicon solar cell is inhibited by high contact resistance. By plating the SCF with metal, a new SCF cell concept known as the “Advanced SCF” (AdvSCF) cell that can resolve the contact resistance problem is presented. In the first AdvSCF cells demonstrated in this work, the nickel (Ni) plating coverage across the cell was found to be non-uniform with Ni voids mostly concentrated around the busbar. This was found to be avoidable by ensuring that the spin-on phosphoric acid dopant layer was uniformly thick across the whole cell area and especially at the busbar. With uniform Ni plating coverage achieved, in a batch of 6 AdvSCF cells, an average batch efficiency of 18.40 % was achieved with the highest at 18.82 %. This was achieved without any experimental optimization of the front grid design or other cell properties, implying that there is potential to achieve significantly higher efficiency levels.