To address the limitation of a DRAM-based single-tier in satisfying the comprehensive demands of main memory, multi-tiered memory systems are gaining widespread adoption. To support these systems, operating-system-level solutions that analyze the application's memory access patterns and ensure data placement in the appropriate memory tier have been vastly explored. In this paper, we identify reinforcement learning (RL) as an effective solution for tiered memory management, and its policy can be formulated in a solvable form using RL. We also demonstrate that an effective region-granularity memory access monitoring method is necessary to provide an accurate environment state to the RL model. Thus, we propose IDT, an intelligent data placement for multi-tiered main memory. IDT incorporates an RL-based demotion policy autotuning and a mechanism that efficiently demotes cold pages to lower-tier memory. IDT also promotes hot pages to upper-tier memory to minimize access on slow memory, featuring a lightweight machine learning algorithm. IDT employs region-granularity memory access monitoring with statistical-testing-based adjacent region merge and split to improve precision and mitigate ambiguity observed in priorworks. Experiments on an actual four-tiered memory system show that IDT achieves an average 2.08x speedup over the default Linux kernel and 11.2% performance improvement compared to the state-of-the-art solution.

Tiered memory using DRAM as upper-tier (fast memory) and emerging slower-but-larger byte-addressable memory as lower-tier (slow memory) is a promising approach to expanding main-memory capacity. Based on the observation that there are many cold pages in data-center applications, proactive demotion schemes demote cold pages to slow memory even when free space in fast memory is not deficient. Prior works on proactive demotion lower the requirement of expensive fast-memory capacity by reducing applications’ resident set size in fast memory. Also, some of the prior works mitigate the massive performance drop due to insufficient fast-memory capacity when there is a spike in demand for hot data. However, there is room for further improvement to save a larger fast-memory capacity with further aggressive demotion, which can fully reap the aforementioned advantages of proactive demotion. In this paper, we propose a new proactive demotion scheme, ADT, which performs a ggressive d emotion and promotion for t iered memory. Using the memory access locality within the unit in which applications and memory allocators allocate memory, ADT extends the unit of demotion/promotion from the page adopted by prior works to make its demotion more aggressive. By performing demotion and promotion by the extended unit, ADT reduces 29% of fast-memory usage with only a 2.3% performance drop. Also, it achieves 2.28× speedup compared to the default Linux kernel when the system's memory usage is larger than fast-memory capacity, which outperforms state-of-the-art schemes for tiered memory management.

Compute Express Link (CXL)를 통해 CPU와 연결된 메모리(CXL 메모리)는 메인 메모리 용량을 확장할 방안으로 주목받고 있다. CXL 메모리를 효과적으로 활용하기 위해서는 프로그램의 메모리 접근을 추적하고 데이터를 CPU에 직접 연결된 메모리(로컬 메모리)와 CXL 메모리 중 적절한 장치에 배치해야 한다. 본 논문에서는 소프트웨어 기반 메모리 접근 추적의 성능 부담을 완화하고 CPU 수정에 따른 비용을 줄이기 위해, 기존 연구들에서는 널리 고려되지 않았던 CXL 메모리 장치 내부의 메모리 컨트롤러(CXL 단 메모리 컨트롤러)에 주목한다. 본 논문에서 제안한 기법은 CXL 단 메모리 컨트롤러에 추가 된 간단한 하드웨어 로직을 통해 메모리 접근을 추적하고, 이를 활용하여 확률적으로 데이터를 로컬 메모리에 배치(승격)한다. 제안한 기법은 기본 Linux kernel 대비 최대 12.5%, 최신 소프트웨어 기반 연구 대비 최대 2.1%의 성능 향상을 보여준다.

In this paper, we identify new partial data redundancy among multiple cache lines that are not exploited by traditional memory compression or memory deduplication. We propose Base and Compressed Difference (BCD) deduplication that effectively utilizes the partial matches among cache lines through a novel combination of compression and deduplication to increase the effective capacity of main memory. Experimental results show that BCD achieves the average compression ratio of 1.94× for SPEC2017, DaCapo, TPC-DS, and TPC-H, which is 48.4% higher than the best prior work. We also present an efficient implementation of BCD in a modern memory hierarchy, which compresses data in both the last-level cache (LLC) and main memory with modest area overhead. Even with additional meta-data accesses and compression/deduplication operations, cycle-level simulations show that BCD improves the performance of the SPEC2017 benchmarks by 2.7% on average because it increases the effective capacity of the LLC. Overall, the results show that BCD can significantly increase the capacity of main memory with little performance overhead.

Hardware performance monitoring units (PMUs) are a standard feature in modern microprocessors, providing a rich set of microarchitectural event samplers. Recently, numerous profile-guided optimization (PGO) frameworks have exploited them to feature much lower profiling overhead compared to conventional instrumentation-based frameworks. However, existing PGO frameworks mainly focus on optimizing the layout of binaries; they overlook rich information provided by the PMU about data access behaviors over the memory hierarchy. Thus, we propose MaPHeA, a lightweight Memory hierarchy-aware Profile-guided Heap Allocation framework applicable to both HPC and embedded systems. MaPHeA guides and applies the optimized allocation of dynamically allocated heap objects with very low profiling overhead and without additional user intervention to improve application performance. To demonstrate the effectiveness of MaPHeA, we apply it to optimizing heap object allocation in an emerging DRAM-NVM heterogeneous memory system (HMS), selective huge-page utilization, and controlling the cacheability of the objects with the low temporal locality. In an HMS, by identifying and placing frequently accessed heap objects to the fast DRAM region, MaPHeA improves the performance of memory-intensive graph-processing and Redis workloads by 56.0% on average over the default configuration that uses DRAM as a hardware-managed cache of slow NVM. By identifying large heap objects that cause frequent TLB misses and allocating them to huge pages, MaPHeA increases the performance of the read and update operations of Redis by 10.6% over the transparent huge-page implementation of Linux. Also, by distinguishing the objects that cause cache pollution due to their low temporal locality and applying write-combining to them, MaPHeA improves the performance of STREAM and RADIX workloads by 20.0% on average over the system without cacheability control.

차세대 비휘발성 메모리(Non-Volatile Memory)는 DRAM 용량 확장 한계의 대안 중 하나로 제시되어 활발히 연구되어 왔으며, 최근 Intel 사에서는 비휘발성 메모리 제품인 Optane DC Persistent Memory (DCPMM)를 출시하였다. 최신 Intel 서버는 DCPMM을 활용하기 위해 DCPMM을 메인 메모리, DRAM을 DCPMM의 캐시로 사용하는 Memory mode와, DCPMM과 DRAM을 독립적인 메모리로 사용하는 App Direct mode를 제공한다. 본 논문에서는 두 가지 동작 방식들의 성능을 비교하여, 응용프로그램의 워킹 셋 크기가 DRAM 크기보다 클수록 DRAM 캐시 미스 페널티(~70ns)로 인해 데이터를 DCPMM에만 할당한 경우보다 오히려 성능이 감소하는 것을 확인하였다. 이를 통해, Memory mode에서는 응용프로그램의 워킹 셋 크기가 DRAM 캐시보다 작거나 데이터 지역성이 보장되면 상대적으로 느린 DCPMM 접근에 따른 성능 감소를 최소화할 수 있으나, DRAM 캐시 미스 페널티로 인해 워킹 셋이 크고 데이터 지역성이 없는 환경에서는 App Direct mode를 사용하는 것이 성능 측면에서 더 유리할 수 있음을 보인다.