Integrated circuits (ICs) connected to a universal serial bus (USB) interface require robust electrostatic discharge (ESD) protection strategies due to the nature of the high-speed interface and the regular access by users. System-efficient ESD design (SEED) simulations can help predict the level of ESD stress seen by the IC when protected by a transient voltage suppressor (TVS). In the following paper, previously developed models were improved to predict the voltage and current seen by a TVS and an on-chip protection diode when an ESD gun was discharged to one USB cable pin. Models were improved, in part, by accurately modeling the conductivity modulation within the behavioral TVS model and by using a measured equivalent source to represent the complex interaction between the ESD gun, USB cable, and enclosure. The response of the TVS and on-chip diode was studied in simulation and measurement for several cable configurations and when adding passive components between the TVS and on-chip diode. Simulations predicted peak and quasi-static voltages and currents at the TVS and on-chip diode within 30% of those seen in measurements. The proposed modeling process can help engineers to evaluate and optimize the effectiveness of their ESD protection strategies under complicated test conditions.

A simplified physics-based model for predicting the transient response and self-heating behavior of silicon-controlled rectifier (SCR) snapback-type transient voltage suppressors (TVS) is presented. Comparisons of the predicted quasi-static behavior and transient waveforms with measurements suggest that the proposed model accurately captures the most important characteristics of the device. Its simplified nature means it can be easily tuned using only data obtained from package-level measurements.

A simplified physical-based model for deep-snapback transient voltage suppressors (TVS) is developed in this article. While based on physics, the number of parameters and components is minimized, so the model can be tuned easily from available measurements of the packaged TVS. SPICE convergence issues seen in previous snapback device models are eliminated by adding nonlinear damping components to the model. No convergence issues were seen among any of the simulations performed for this study, which includes transmission-line pulse tests with multiple levels and rise times. The proposed model was used to represent two different TVS devices and was validated in both device- and system-level simulations. Simulations of quasi-static and transient behavior matched measurement results within about 20% among all the tested cases.

Spring clips and fabric-over-foams (FOFs) are widely used in mobile devices for electrical connection purposes. However, the imperfect metallic connections tend to induce passive intermodulation (PIM), resulting in a receiver sensitivity degradation, known as RP desensitization. Due to the complexity of the PIM characterization, there is not yet a way to evaluate PIM performance using a simple setup for environments like factories. In this paper, a current-voltage (I-V) behavior-based PIM evaluation method is proposed and validated with various metallic contacts and contact forces. The test results demonstrated the feasibility of the PIM performance evaluation based on the measured static I-V curve.

Accurate models of transient voltage suppression (TVS) devices are important for determining the suitability of electrostatic discharge (ESD) protection strategies early in the design process. An improved TVS model is used in the following paper to represent a variety of TVS devices, including a snapback device, non-snapback device, and a varistor. The models include recent improvements to represent conductivity modulation and the overall shape of the TVS device's transient response. The models are tuned based on characterizations of these protection devices using a transmission line pulse (TLP), and are then used in a system efficient ESD design (SEED) simulation to predict the transient voltages and currents in a system consisting of an off-chip TVS, an IC with on-chip ESD protection, and a PCB trace in between. Simulated transient voltage and current waveforms closely match measurements both when testing the TVS devices by themselves and in SEED simulations. Peak and quasistatic currents through the TVS and on-chip diode were typically captured within about 10% or less across the devices tested while varying both the rise time and level of the injected TLP.

A method for calculating the peak voltage at the input of the IC is presented for an I/O port subsystem consisting of a TVS protection device, an IC on-chip protection and a PCB trace. The method is valid for non-snapback on-chip protection where the silicon part can be fully described by a quasistatic (VF)-TLP curve and allows to determine the peak voltage from measurement data of the individual components only.

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and on -chip diode, where the diode's turn on may prevent turn on of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn on , and on -chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn on . Adding a small passive impedance between the external TVS and the on -chip diode helps the TVS turn on and reduce the current through the on -chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce on -chip diode current by up to a factor of two.

In modern consumer electronic devices, for the purpose of having easier access for assembly and repair in a compact designed product, metallic connection components such as springs are universally used for metallic connections between modules or chassis. However, the non-ideal metallic connections tend to have a certain level of non-linearity. Therefore, significant attention has been aroused recently because the passive-intermodulation (PIM) can degrade the radio-frequency (RF) antennas’ receiving quality especially when the unsatisfying spring connections are placed near the RF antenna. Typically, advanced and expensive instruments and components are required to estimate the non-linearity levels of the springs. However, those instruments are usually not available for the manufacturing factories for massive tests. This paper is focused on investigating the feasibility of estimating the nonlinearity level of spring contacts using DC resistance (DCR), which has easier access to be tested with much lower cost. Study showed that the DCR, when under certain conditions, can serve as the alternative figure of merit for PIM prediction. Then, the Gaussian process regression (GPR) analysis based on measured data can provide a statistical estimation to the generated PIM from the DCR values.

Passive intermodulation (PIM) is one of the most common nonlinear behavior that exists in a variety of applications. Nowadays, consumer electronics designs use a variety of mechanical features for radio-frequency (RF) antenna feeds and grounding, such as springs, gaskets, screws, etc. When these components are placed in the path or nearby the RF antennas, the unsatisfying connection such as loose contact will generate PIM and create noise in the receiving frequency range. This can potentially cause RF desense issues. In product design, the most intrinsic method to improve the electrical connection is applying more compression between the spring tip and the landing substrate, but seldom will the engineers notice the spring structure itself can also introduce a lot of PIM. This paper concentrates on characterizing and validating the captured RF springs that can introduce noticeable PIM due to its structural self-contact phenomenon. An integrated camera recorded the spring side-view under compression. The measured information indicates that high PIM tends to occur when the spring contacts itself unintentionally.

Modeling ESD protection using the System Efficient ESD Design (SEED) methodology enables optimal protection of an IO using TVS and external components. The success of modeling depends on the accuracy of the models. This work shows improvements to SPICE models used to characterize TVS diodes and IC I/O. The improvement is twofold. The transition phases between snapback and main current flow have been adjusted to achieve realistic waveforms for the rise times from 500 ps to 5 ns in a voltage range from Vt1 to the high current region, and complex curvatures of the IV curve are included. The model is capable of operating in generic SPICE and being tested in ADS and LT-SPICE. The paper explains this in detail to enable the reader to apply this modeling principle.

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn-on behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn-on behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

Performance of electromagnetic interference (EMI) filters in power-electronics applications is limited by the parasitic coupling between the components of the filters and the self-parasitic of each component. While these parasitic effects can be partially taken into account on the circuit level, it is difficult to estimate their values. In this article, a full-wave modeling methodology is proposed to predict the performance of a complete EMI filter up to 1 GHz. Following the proposed methodology, the mutual couplings among the EMI filter components are taken into account as well as the self-parasitics of each individual component. Experiments and simulations are carried out to validate the modeling methodology. A self-parasitic cancellation technique is also applied to demonstrate the benefits of three-dimensional modeling methodology in EMI filter design.

The ESD coupling path and on-board impedances strongly affect the ESD rise time seen on a PCB trace. Possible race conditions between external and on-die ESD protection were studied using measurement-based models of the transient response and on-board passives. Results show the interplay of rise time and protection turn-on can prevent the external TVS from responding in time.

Electrohydrodynamics is commonly used in microfluidics to control and manipulate the fluid. Though there are studies on the rotation flow in suspended films, the thin film liquid is easily broken and cannot last long hence not applicable in specific applications. Here, we established a three-dimensional microchamber embedded with two pairs of microelectrodes to investigate the rotational phenomenon of bulk of liquid which we called 'water fan' effect based on the electrohydrodynamics force. When proper voltages were applied on these microelectrodes, the tornado-like rotation would be generated. Both the numerical and experimental results showed that the controllable and continuous rotation could be achieved in the microchamber. In addition, the concentration effect resulting from the rotation flow was also observed. The proposed method offers great promises in providing theoretical and practical guideline in microfluidic devices for mixing, separating, and cooling applications.

In recent years, researchers are paying the increasing attention to the development of portable microfluidic diagnostic devices including microfluidic flow cytometry for the point-of-care testing. Microfluidic flow cytometry, where microfluidics and flow cytometry work together to realize novel functionalities on the microchip, provides a powerful tool for measuring the multiple characteristics of biological samples. The development of a portable, low-cost, and compact flow cytometer can benefit the health care in underserved areas such as Africa or Asia. In this article, we review recent advancements of microfluidics including sample pumping, focusing and sorting, novel detection approaches, and data analysis in the field of flow cytometry. The challenge of microfluidic flow cytometry is also examined briefly.