Inspired by the Roman "two-faced god" Janus, a heterogeneous ultrasonic transducer is proposed with double-sided 1-3 piezoelectric composites, exhibiting bidirectional acoustic radiation and matching. The transducer features a "dense-monolithic-sparse" distribution, optimizing acoustic impedance matching and enhancing electroacoustic energy conversion efficiency in the thickness direction. Finite element simulations confirm its superior vibration mode performance. The Janus transducer maintains a high electromechanical coupling coefficient and wide bandwidth while achieving an improved echo voltage amplitude (∼3.35 V). Furthermore, it enables high-quality photoacoustic imaging through fabricated transducers, validating its exceptional performance. The proposed heterogeneous composite design offers an effective approach for high-performance ultrasonic transducers and their application in underwater ultrasonic imaging and photoacoustic imaging.

High-frequency ultrasound imaging, due to its penetrability and micrometer-level resolution, is a critical modality for nondestructive testing (NDT) of integrated circuit (IC) packaging. However, the substantial acoustic impedance mismatch between the coupling medium (water) and the silicon substrate creates a severe measurement bottleneck: strong surface reflections drastically reduce the energy transmitted into the chip, degrading the signal-to-noise ratio (SNR) and resolution of internal interconnects. To overcome this physical limitation and enhance the measurement capability of scanning acoustic microscopy (SAM), we have designed a precise anti-reflection coating based on the theory of the evolution from electromagnetic transmission lines to acoustic transmission lines. By modeling the acoustic propagation path as an equivalent circuit, we designed and fabricated a three-layer composite structure (Parylene C/Au/Parylene C) specifically optimized for the particular frequency (70 MHz in this study). Experimental validation on commercial IC chips demonstrates that this "instrumentation conditioning" approach significantly improves signal integrity. Specifically, the coating yielded a 52% increase in the amplitude of internal echoes (from 142 to 216 mV). Furthermore, C-scan imaging revealed a 93% average improvement in the mean gradient of internal metal wires across multiple layers, enabling high-fidelity 3-D reconstruction of interconnection structures that were previously indistinguishable from noise. This method offers a robust, low-cost solution to the intrinsic attenuation problem in high-frequency acoustic measurement, significantly extending the detection depth and clarity for IC reliability analysis.

With the continuous evolution of CMOS technology towards deep sub-micron and advanced nodes, the challenges of analog integrated circuits (ICs) in performance, design efficiency, and reliability are increasingly prominent. The traditional design methods that rely on manual experience and repeated simulations are no longer able to meet the requirements of complex systems for high performance, high robustness, and fast iteration. In this research, the efficient and robust optimization design methods for analog ICs are systematically reviewed. Firstly, the representative efficient design methods on topology synthesis, parameter optimization, and transfer learning are studied. In addition, with the advancement of technology and the reduction of power supply voltage, parasitic effects and the influence of the external environment on circuits can no longer be ignored. Thus, the robust optimization design methods that consider process, voltage, temperature (PVT), and parasitic effects are further investigated. Then, the advantages and limitations of different methods on design efficiency, performance, and reliability are compared and discussed. Finally, an outlook on the development trend of the efficient and robust design methods for analog ICs is provided, which can provide a reference for subsequent research and engineering applications.

With the continuous improvement of three dimensional (3D) integrated technology, the electrical-thermal coupling problem inside vias has become increasingly prominent. However, most current studies on substrate vias focus on a single physical field and do not take into account the changes in material parameters caused by electrical-thermal effects. To address this problem, this paper proposes an electrical-thermal coupling model suitable for vias structure in multilayer high temperature co-fired ceramic (HTCC) substrate. Utilizing the equivalent electrical circuit (EEC) model and the equivalent thermal circuit (ETC) model, and describing the temperature-varying components in the equivalent models with Verilog-A language, the method enables the solution of temperatures for vias in different layers. This method introduces the coupling of material coefficients with temperature, which increases the simulation speed by more than 30 % compared to traditional finite element methods. Moreover, within the 0-50 GHz frequency band, the steady state temperature error at the center of the via is within 3 %. This indicates that the model proposed in this paper can quickly obtain the temperature changes of the via while ensuring accuracy.

This paper presents a 2-GS/s voltage-time hybrid pipelined analog-to-digital converter (ADC) with a 14-bit digital output, implemented in a 28-nm CMOS process. To alleviate the gain-bandwidth-power trade-off in deeply scaled technologies, the proposed architecture employs a SHA-less front-end and a low-gain inverter-based push-pull RA for energy-efficient coarse quantization. The residue is then transferred to the time domain via a highly linear constant-current voltage-to-time converter (CC-VTC) and digitized by a four-channel time-interleaved gated-ring-oscillator (GRO) TDC. To recover dynamic linearity degraded by low-gain amplification and interleaving mismatches, a multiplier-less digital background calibration engine is implemented. Leveraging mean absolute value (MAV) statistics and dither-injected least-mean-squares (LMS) algorithms, it effectively compensates for inter-channel and interstage errors with minimal hardware overhead. The prototype occupies an active area of 0.16 mm2. At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC.

Cryogenic fractional-N phase-locked loops (PLLs) are essential for large-scale superconducting quantum computing, and serve as integrated pump sources for Josephson parametric amplifiers. These PLLs enable high-fidelity qubit readout while reducing the thermal load and wiring complexity associated with room-temperature generators. However, the cryogenic pump sources developed thus far were unable to meet the stringent phase noise and frequency agility requirements for high-fidelity qubit readout. In this study, we present a cryo-CMOS fractional-N charge-pump PLL (CP-PLL) operating over a range of 4-300 K that provides low-noise, multi-frequency pump and clock signals. We proposed an automatic bleed calibration (ABC) technique to mitigate the folding effect of the delta-sigma (Delta Sigma) modulator residue through phase-frequency detector (PFD) and CP nonidealities. This approach helps in detecting PFD pulsewidth asymmetry and digitally optimizing the bleed current, thereby minimizing both the reference and fractional spurs. The proposed prototype was fabricated via a 28-nm CMOS process and synthesizes signals ranging from 0.1 to 44 GHz using on-chip dividers and multipliers. At 4 K, it achieves integrated jitter (12 kHz-20 MHz) of 19.4 fs under a frequency of 8.6 GHz, with reference spurs below-71 dBc and fractional-spur suppression of up to 40 dB when ABC is enabled. At 300 K, the proposed CP-PLL achieves a jitter of 29.7 fs under a frequency of 8.6 GHz with a reference spur of-82 dBc. To the best of our knowledge, this represents the lowest jitter reported for a cryo-CMOS fractional-N CP-PLL in the literature.

This paper presents a 16-bit 16-channel +/- 5 V/+/- 10 V/-10 V - 6 V/-16 V - 10 V/-12 V - 14 V/-10 V - 0 V/-16 V - 0 V/-20 V - 0 V high-voltage digital-to-analog converter (DAC) with 40 mA current capability in 180 nm Bipolar-CMOS-DMOS (BCD) process. It incorporates a 2-channel analog dither input that is designed for Mach-Zehnder modulator auto-bias control. A novel R-string layout and a two-stage switching sequence are implemented to achieve high-resolution and calibration-free operation with common poly resistors rather than thin-film resistors. The second stage DAC-embedded amplifier adopts a proposed adaptive bias to maintain an almost constant Vds for the input differential pairs, resulting in higher linearity when operating in a high-voltage domain. The measured integral non-linearity (INL) is <12 least significant bit (LSB) and the differential non-linearity (DNL) is <3 LSB as the temperature shifts from -40 degrees C to 125 degrees C, respectively. The zero-output noise is below 250 mu Vpp, corresponding to a root mean square noise of less than 37 mu Vrms. The mean zero-output voltage changes from -800 mu V to 0 V as the temperature increases from -40 degrees C to 125 degrees C. The gain error across 16 channels is below 0.25% FS, and the setup time is less than 16 mu s with a load capacitance of up to 1 nF. The K error is nearly 0, when the proposed auto-bias control is locked. And the output optical power varies by only 0.02 dBm in 40 min with the proposed auto-bias control.

This paper presents a novel 2- to 18-GHz vector-sum phase shifter (VSPS), fabricated in 0.13-mu m SiGe BiCMOS technology, that employs a reconfigurable polyphase filter (PPF). In the proposed design, the fixed capacitors in the PPF network are replaced with varactors, providing tunable characteristics while preserving phase accuracy. A high-precision variable gain amplifier (VGA) in the final synthesis stage further improves the phase-shifting accuracy. Measurements show an RMS phase error below 1.5 degrees and an RMS gain error under 1.2 dB across the full 2- to 18-GHz band. The phase shifter achieves a low power consumption of 105 mW at a 3.3-V supply and occupies a compact area of 1240 x 860 mu m2.Trial Registration: Not applicable. This work does not involve clinical trials

Crosstalk, a detrimental phenomenon in ultrasonic arrays, compromises resolution, penetration depth, and diagnostic reliability. This study examines the impact of kerf filling materials on crosstalk suppression and imaging performance via integrated numerical simulations and experimental validation. Two fillers with contrasting acoustic properties were evaluated: rigid epoxy resin (Epo-Tek 301) and soft silicone rubber (RTV-664). RTV-664, exhibiting lower acoustic impedance and higher attenuation, demonstrated reduced mechanical coupling between adjacent elements. To validate this, a 128-element linear array was designed and fabricated, with its electrical, transceiver, and crosstalk characteristics systematically assessed through finite element simulations, phantom experiments, and "in vivo" imaging. Results indicate that RTV-664 reduced crosstalk in first- to third-order adjacent elements by an average of 33.4% across the 4-8 MHz bandwidth, aligning with simulated predictions. Imaging tests further confirmed that RTV-664-based arrays achieved broader bandwidth, enhanced field uniformity, and superior image quality, including improved resolution, penetration depth, signal-to-noise ratio (SNR), and contrast-to-noise ratio (CNR). These findings underscore the critical role of kerf filling materials selection in crosstalk mitigation, offering theoretical insights and experimental evidence for optimizing ultrasonic array design toward high-performance medical imaging.

The massive growth of data has brought vigorous vitality to the Internet of Things (IoT). It has also brought new challenges, such as confidentiality privacy protection and redundant data transmission. Concerning this regard, data aggregation serves as an efficient technique to minimize the transmission frequency among massive objects in smart grid (SG). By aggregating a large amount of encrypted data from distributed IoT devices, the proposed framework enables efficient and privacy-preserving analytics at the edge. With the advent of the postquantum era, a good aggregation scheme must provide quantum resistance while ensuring the secure aggregation of ciphertext power data. However, the excessive overhead limits anti-quantum algorithms from being widely used in SG, where resource devices are limited. Therefore, it is an important part of the current private data security aggregation technology to find a low cost and lightweight inverse quantum algorithm to achieve user data security aggregation. In this article, we propose an improved NTRU-based cryptosystem with multidimensional coding, referred to as multidimensional coding NTRU (MC-NTRU), and use the lattice batch signature technique, which improves the efficiency of the scheme while satisfying the anti-quantum attack. Based on these, we design the multidimensional auditable lattice-based privacy-preserving data aggregation scheme (MA-PPDA) for privacy data on resource-limited IoT devices, such as SGs. In addition to this, the scheme achieves fault tolerance (FT) of the scheme by adding zeros and random numbers to the user data. The comparative study against the existing approaches demonstrates that the proposed scheme not only adheres to critical security aspects, including user privacy, data confidentiality, integrity, and authenticity, but also decreases both communication and computational burdens on the system. This makes our scheme particularly apt for IoT environments characterized by constrained device resources.

Abstract Ultrasonic transducers have long relied on lead-based piezoelectric materials. However, the potential harm of lead to the environment and human health has spurred an urgent demand for environmentally friendly lead-free alternative materials. Bismuth sodium titanate (BNT) is regarded as a promising piezoelectric material for lead-free transducers due to its low dielectric constant and acoustic impedance. To address the problem that the previously developed 0.84BNT-0.133BKT-0.027BT composition still struggles to meet the requirements of high-quality biological tissue imaging, this study adopted an acceptor doping strategy and prepared a B-site Fe3+-doped lead-free piezoceramic system. The results show that appropriate Fe3+ doping produces a favorable balance between R3c/P4bm phase-structure modification and defect-related pinning, thereby enhancing the electromechanical response. At x = 0.01, the piezoelectric coefficient reaches the maximum value of 180 pC/N, while kt reaches 0.42, indicating enhanced thickness-mode electromechanical coupling. The planar 10 MHz ultrasonic transducer fabricated with this composition exhibits high sensitivity, with an insertion loss |IL| of 16 dB. After introducing an acoustic focusing lens, the focused transducer achieves axial and lateral resolutions of 182 and 264 μm, respectively. In addition, clear imaging of the internal structure of a porcine eyeball and the surface of a commemorative coin was successfully achieved. These results confirm that the B-site Fe3+-doped modified BNT-BKT-BT ternary lead-free ceramic has great application potential in high-performance environmentally friendly medical ultrasonic transducers.

This paper reports a method to achieve more stable data storage functionality by adjusting the forming compliance current (FCC) and set compliance current (SCC) of Pt/SiNx/Ti RRAM. Based on electrical tests and current conduction mechanism analysis, it is proposed that the relatively low FCC is conducive to forming a dominant single conductive filament and SCC has a significant impact on the formation process and the nitridation degree of the interface layer. Both of two types compliance current are crucial for improving the cycle-to-cycle (C2C) stability. It is worth noting that we have recently applied this method to test HfOx-based RRAM to improve its C2C stability, which demonstrates the universality of the method. This paper provides a powerful insights for enhancing the C2C stability of RRAM.

High-Resolution Analog-to-Digital Converters (ADCs) are essential for ultrasonic color Doppler imaging to accurately capture weak blood signals. However, the current design methods for ADC rely heavily on design experience, which leads to low efficiency and long design cycles. A high-efficiency two-stage optimization framework for high-resolution ADC is proposed in this research based on the PSO and RL algorithm. During the optimization, an improved Convolutional Neural Network (CNN) model is trained to obtain the real-time circuit performance metrics. To verify the effectiveness of the proposed method, 16-bit SAR ADC and LDO circuits in the overall ADC system are selected to be optimized by the proposed method. The simulation results show that the optimized SAR ADC can achieve a Signal to Noise and Distortion Ratio (SNDR) of 97.1 dB, and an Effective Number of Bits (ENOB) of 15.81 bits in 1 MHz bandwidth with the LMS adaptive background calibration. Compared with the advanced RL-based optimization design method, the online optimization time of LDO and SAR ADC can be decreased by at least 7.2% and 90.6% respectively. The optimized power consumption of LDO and SAR ADC can be decreased by at least 11% and 40% respectively. Then, the system-level simulation is conducted based on Field II. The simulation results of blood flow evaluation datasets obtained by 12-bit and 16-bit ADCs demonstrate that the optimized 16-bit ADC provides promising overall performance in term of image contrast and blood velocity estimation accuracy. Thus, the proposed optimization method has the potential to improve the design efficiency and performance of ADC system in the ultrasonic color Doppler imaging. In our future research, the ADC will be taped out, and the experimental characterization of fabricated hardware will be conducted.

In three-dimensional integrated circuits (3-D ICs), through-silicon vias (TSVs) are subject to significant thermal stress due to mismatches in the coefficients of thermal expansion (CTE) among constituent materials, which severely compromises device reliability. Grounded in thermoelastic theory, this paper presents a high-precision analytical model for predicting transient thermal stress in TSVs. First, an analytical solution for the transient temperature field within TSVs is derived using heat conduction theory in a cylindrical coordinate system. Subsequently, by incorporating the thermoelastic displacement potential and Love's displacement function, a closed-form analytical model for transient thermal stress is formulated. The model further accounts for axial third-kind thermal boundary conditions and incorporates temperature-dependent material properties to enhance physical realism. Validation against COMSOL multiphysics simulations demonstrates that the maximum relative error and maximum absolute error in the predicted transient temperature field remain below 1.2 % and 0.4 K, respectively, while the corresponding errors for von Mises stress are within 1.6 % and 0.8 MPa. Notably, the computational efficiency of the proposed model exceeds that of the finite element method (FEM) by approximately two orders of magnitude. Moreover, it exhibits strong adaptability across a wide range of material combinations and geometric configurations. We further employ the analytical model to investigate the effect of thermal stress on carrier mobility in TSVs and the stress interaction between adjacent TSVs. In comparison with classical 2-D Lame solutions and 3-D Kane-Mindlin theory, the proposed model achieves superior accuracy without relying on empirical correction factors and effectively captures the spatial distribution of thermal stress in TSVs under transient thermal conditions. This study confirms that the developed analytical model offers exceptional accuracy and efficiency in characterizing transient thermal stress distributions in 3-D IC TSVs, thereby providing a robust and precise tool for thermomechanical reliability assessment and design optimization.

This study employed a conventional solid-state sintering method to prepare a series of Bi-Li co-doped (1-x) (Ba0.94Ca0.06)(Ti0.93Sn0.07)O3-x(Bi0.5Li0.5TiO3)(x = 0-0.003) lead-free piezoelectric ceramics using the conventional solid-phase sintering process. The effects of Bi and Li elements on the microstructure and piezoelectric properties of the ceramics were investigated. Experimental results indicate that Bi and Li doping enhances the ceramic's relaxation characteristics and effectively improves the electrical properties of the ceramic matrix. At x = 0.002, the ceramic exhibits optimal comprehensive properties: the piezoelectric constant d33 = 230 pC/N, the Curie temperature Tc = 69 degrees C, the radial electromechanical coupling coefficient kp = 0.25, the thickness vibration electromechanical coupling coefficient kt = 0.25, and the sound velocity c = 5470 m/s. A planar 10 MHz ultrasonic transducer was fabricated using BCTS-0.002BLT, exhibiting the peak-to-peak pulse-echo signal Vpp of 78.67 mV, the center frequency fc of 12 MHz, the -6 dB bandwidth of 34.2%, and the lateral resolution Rlateral of 1.06 mm, which generally matched simulation results. After focusing, the transducer's Vpp increased to 175.3 mV, the center frequency fc rose to 11.2 MHz, the -6 dB bandwidth expanded to 37.7%, and lateral resolution Rlateral improved to 0.74 mm. Coin and porcine eyeball imaging tests demonstrated clear coin edge delineation with well-preserved digital details. In biological imaging of a pig eyeball specimen, the internal structures (including the conjunctiva, cornea, and lens) were well-visualized, demonstrating its potential applications in non-destructive testing and bioimaging.

High-frequency ultrasonic transducers are pivotal for detecting minute defects, offering distinct advantages in terms of non-destructive evaluation, non-invasiveness, and superior spatial resolution. However, achieving effective focusing and efficient acoustic transmission for ultra-high-frequency ultrasonic transducers is a significant challenge. To address this challenge, a mass-spring acoustic matching layer is designed for a transducer based on a half-concave LiNbO3 piezoelectric element at 100 MHz. The proposed mass-spring stack, comprising a 0.25 μm Au layer and a 2.5 μm Parylene-C layer, operates within a deposition-friendly thickness range ideal for curved substrates, while a conventional quarter-wavelength Parylene-C layer would necessitate a thickness of 6.0 μm at this frequency. The transducer is modeled in COMSOL Multiphysics 6.1, coupling solid mechanics, electrostatics with piezoelectric effects, and pressure acoustics for the water load. Using a fixed concave geometry (curvature radius is 1 mm, which means the focal length is also 1 mm), a frequency sweep from 50 MHz to 150 MHz is conducted to evaluate performance. Analysis of the pressure distribution in the focal plane reveals that the focal length and the -6 dB beamwidth are predominantly governed by aperture diffraction and exhibit minimal variation upon incorporation of a matching layer. The focal length is approximately 1.02 mm within the excitation frequency range of 70 MHz-150 MHz, and the beamwidth decreases markedly with increasing frequency. At 100 MHz, the measured -6 dB beamwidth is approximately 31.6 μm without a matching layer, 32.3 μm with a quarter-wavelength matching layer, and 31.0 μm with a mass-spring matching layer. Crucially, quantitative comparisons reveal that this design yields a systematically higher focal pressure; near the 100 MHz design frequency, the acoustic pressure amplitude achieved with the mass-spring configuration is 1.5 times greater than that obtained using the quarter-wavelength reference. These research results provide a theoretical basis for the application of ultra-high-frequency ultrasound in the detection of tiny defects.

This paper presents a reconfigurable filter that combines high linearity, low insertion loss, and sharp frequency selectivity, making it well suited for very high frequency (VHF) and ultra-high frequency (UHF) wireless communications. The design leverages high Q on substrate inductors, and by jointly optimizing these inductors with the chip package, it markedly improves key metrics such as selectivity and loss insertion. Fabricated in a 180 nm CMOS process, the die measures 6.29 * 6.29 mm2 and is packaged in a 22.6 * 22.6 mm2 module. Measurements confirm operation from 30 to 700 MHz with a tunable relative bandwidth of 7% to 11%. In a representative configuration, the filter exhibits 5 dB insertion loss, an input 0.1 dB compression point (IP0.1dB) of 23 dBm, and an input third order intercept (IIP3) of 30 dBm, demonstrating excellent linearity and frequency reconfigurability across the entire band.