Clustering single-bit flip-flops (SBFFs) into multi-bit flip-flops (MBFFs) effectively reduces power and area. However, excessive displacement during the clustering and legalization process may incur significant timing degradation. To address this issue, we propose the first comprehensive MBFF placement methodology that addresses excessive displacement caused by pre-placed cells during clustering and legalization while simultaneously optimizing timing, power, area, and bin utilization. Our methodology includes three main features: (1) a force model to relocate flip-flops and reduce timing violations, (2) a clustering and legalization process to reduce timing degradation caused by displacement, and (3) a multi-objective function to identify flip-flop candidates suitable for MBFF clustering. Our methodology outperforms all participating teams in the 2024 CAD Contest at ICCAD on Power and Timing Optimization Using Multibit Flip-Flops, based on exactly the same settings.

In modern advanced packaging, redistribution layers (RDLs) are often used for signal transmission among chips, and vias are used for communication among different layers. Most existing RDL routers perform via planning before routing. However, since vias can be placed at arbitrary locations under the irregular via structure, via planning limits the solution space and reduces layout flexibility. This work proposes a new flow with a novel routing graph model for 90-and 135-degree routing, which allows dynamic via insertion during routing. The proposed algorithm enlarges the solution space by providing more choices during path-finding, achieving higher routing quality. The experimental results based on commonly used benchmark suites show that our router achieves shorter wirelength and runtime than state-of-the-art works, including an any-angle router.

In modern printed circuit board (PCB) designs, the increasing complexity poses more challenges for automatic placement. Existing PCB placement methods cannot handle complex constraints, especially when dealing with components and pads that are double-sided, heterogeneous, irregularly shaped, arbitrarily oriented, and subject to complex clearance constraints. This paper proposes the first constraint graph-based legalization approach for these constraints. We use a slicing technique to model each component as a set of rectangles, enabling a more accurate geometric representation. Unlike the linear programming method commonly used for macro placement in integrated circuit (IC) design, we employ a mixed integer linear programming (MILP) formulation to effectively expand the solution space. To handle large designs, we incorporate a two-phase coarse-to-fine scheme to facilitate the MILP solving process. Experimental results show that our method achieves an average 43.1% reduction in displacement compared to traditional rectangle-based legalization approaches, while also significantly improving robustness.

The noisy intermediate-scale quantum (NISQ) computer significantly advances quantum computing technology. Due to the physical connectivity constraints of the NISQ device, its induced qubit mapping problem becomes more challenging. Recent works employ heuristics to achieve promising outcomes. However, they are limited to using only one type of center for graph matching, and their exhaustive traversal of the coupling graph results in high computation time. This paper strategically generates specific subgraphs during the initial mapping stage to reduce the solution space for the coupling graph. Then, we employ a bidirectional graph isomorphism search to improve initial mapping. In the main mapping stage, we develop an efficient search algorithm to minimize the number of inserted gates. Experimental results show that our method significantly outperforms the state-of-the-art work in reducing the number of inserted CNOT gates by 13.22% and the runtime by 19.61%.

Automatic printed circuit board (PCB) routing is essential to handle modern PCB designs with fast-growing problem sizes and complicated design constraints. Previous PCB routing studies have two major limitations: they consider uniform wire widths and keep-out distances (clearance rules) across all elements within the same layer. However, in modern PCB design, the mixed layout of high-current power wires and signal wires makes vastly different wire widths and complex clearance conditions issues that need to be addressed. Besides, irregular component shapes and special requirements for power loops impose more challenges. This article presents a new PCB routing algorithm based on A*-search to handle these issues effectively. A frontier-checking method is proposed to efficiently verify whether the grid violates the complex clearance rules of any wire widths during routing. Besides, we propose a scheme to divide multipin nets in order to reduce the total wire length while effectively handling power-related constraints. Experimental results show that our routing algorithm significantly outperforms a state-of-the-art PCB router in terms of routability, total wire length, and runtime. Moreover, our algorithm achieves human-level performance and significantly outperforms Altium on the industrial benchmark.

The mismatch in thermal expansion coefficients among different materials leads to nonuniform deformation in a package, known as warpage. The warpage has become a significant reliability issue in advanced packaging that requires careful management. To address the issue, we have developed a high-fidelity warpage modeling approach that contains preprocessing followed by matrix calculations. This method transforms a 3-D packaging structure into a 2-D thermomechanical coupling problem, simplifying the packaging analysis. We apply finite element methods (FEMs) to the model and obtain the balance between accuracy and efficiency. Experimental results show that our model offers superior accuracy compared to the widely used Suhir's model, achieving average speedups of 11.0 & times; in preprocessing and 12 130 & times; in matrix calculations, with an overall speedup of 233.9 & times; and only 1.0% error compared to the Ansys commercial analysis tool. This high efficiency and accuracy make our model suitable for large-scale optimization, package simulation, and modeling applications.

Modern printed circuit board (PCB) placement involves increasingly complex constraints, including diverse wire widths, irregular component geometries, stringent clearance rules, and intricate power and signal flow requirements. Manual placement under such conditions is time-consuming and error prone. This article presents a constraint-aware placement framework that integrates three key techniques: 1) a simulated-annealing (SA)-based pad alignment method to reduce wire crossings and preserve spacing compliance; 2) a force-directed global placement guided by anchor points extracted from power circuit flows; and 3) a window-based legalization algorithm that ensures overlap removal and rule adherence. Experimental results on real industrial designs demonstrate that our method improves routability by 13.5% and reduces runtime by 26% compared with ePlace-MS. Moreover, our approach outperforms the recent GPU-accelerated PCB placer, Cypress, by over 50% in routability, while delivering complete full-board layouts under practical constraints.

This paper introduces an automated placement framework to optimize component positioning on modern printed circuit boards (PCBs), addressing challenges posed by heterogeneous components, irregular geometries, and complex design rules. The framework employs three key techniques to enhance placement quality and efficiency: (1) a global placement approach integrating collision detection via the Separating Axis Theorem to handle exact component contours and board shapes, (2) a multi-stage force-directed method that dynamically adjusts attractive and repulsive forces to meet clearance and routability constraints, and (3) a scanline-based legalization technique to resolve overlaps and enforce spacing requirements. Our methodology effectively adapts to diverse design limitations and accelerates the process while preserving placement quality. Experimental results demonstrate that our placer significantly improves routability over state-of-the-art solutions, demonstrating robust performance on industrial PCB designs with complex and irregular constraints.

IR drop analysis in the power delivery network (PDN) is crucial for the signoff of integrated circuit (IC) design. Static IR drop significantly affects the IC reliability. Machine learning (ML) has recently been applied to static IR drop prediction for its high accuracy and efficiency. However, most previous works cannot predict with unseen designs, and none can handle different technologies. These problems lead to long training times and data-gathering difficulties, making ML-based methods impractical in the industry. Therefore, a more applicable methodology for static IR drop predictions is needed. This paper proposes a fast, robust, highly technology-transferable image-to-image ML-based methodology for static IR-drop prediction. To enhance transferability and accuracy, we introduce a new input feature, layerwise maps, which encapsulates the PDN network topology well. We further derive a novel generic ML model for various designs and technologies with different numbers of PDN layers. Experimental results demonstrate our methodology's high accuracy, robustness, and technology transferability. We used only ten circuits to tune our pre-trained model on a new technology and achieved an average error rate of 10.4% IR drop value on unseen circuits. Additionally, we tuned our pre-trained model for the 2023 ICCAD CAD Contest. Compared to the contest winner, our method gets a comparable average error rate of 0.000152mV with a run time of less than 1.5 seconds and improves the MAE of the worst case by 29.7%.

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for system-on-chip designs. Recent work in the WRONoC topology designs mainly utilizes crossing switching elements (CSEs) as switching mechanisms on predefined templates. However, using CSEs incurs more microring resonator (MRR) usage and waveguide crossings than parallel switching elements (PSEs), and their predefined templates constrain the solution spaces. To remedy these disadvantages, we propose a fully automated topology design flow that utilizes PSE structures to reduce MRR usage and waveguide crossings. Our add-drop filter sequence model expands the solution space and leverages the advantage of the crossing-free PSE structure. Our fixed-node crossing-aware edge routing effectively minimizes the waveguide crossings, and our A*-search preserves the admissibility property and guarantees an optimal routing solution. Besides, our design flow thoroughly considers the physical layout information. Experimental results show that our design substantially outperforms state-of-the-art works on customized designs.

Placement plays a crucial role in modern chip design, aiming to determine the positions of circuit blocks (macros and standard cells). Traditional data structure-centric heuristics often yield suboptimal placement prototypes, ineffectively guiding downstream mixed-size analytical placement to find the desired results for modern large-scale designs. Recent works have showcased the potential of reinforcement learning (RL) to enhance chip placement by training a policy to place macros as a board game. However, placing macros and fixing them in the earlier stages without sufficient information often incurs undesired solutions. This paper proposes a novel RL-based mixed-size placer with iteratively moving the blocks to characterize dense rewards and comprehensive layout information in each step. We further introduce a semi-concurrent moving mechanism to learn the collaborative dynamics among actions on a subset of blocks at each step. We integrate continuous action spaces to develop a deep Q network-based model for learning the semi-concurrent moving policy to derive the proposed moving strategy. Compared with the state-of-the-art methods, experimental results show that our RL-based placer achieves the best placement quality based on commonly used mixed-size placement benchmarks.

Power distribution networks (PDNs) are designed to deliver sufficient and stable power to circuit components. For high-speed printed circuit boards (PCBs), transient current pulses increasingly affect the power integrity in PDNs, potentially leading to circuit malfunction or component damage. Decoupling capacitors (decaps) are placed on a PDN to ensure power stability. Minimizing the number of decaps becomes critical and has been extensively studied. Traditional heuristic methods often search for unnecessary spaces or get stuck in local minima. To overcome these limitations, we propose an analytical approach that reformulates the nonlinear decap placement problem as an equivalent integer semidefinite programming model. We adopt techniques like integer relaxation and port reduction to improve scalability and minimize the usage of decaps by an adaptive optimization scheme. Experimental results on industrial benchmarks demonstrate that our analytical decap placer achieves better results than the state-of-the-art non-deterministic methods and even significantly outperforms the commercial tool in solution quality and runtime.

This paper presents the first warpage-aware generative learningbased floorplanning algorithm to effectively model the warpage effect and optimize the die floorplan on a fixed outlined substrate. With more heterogeneous materials and dense interconnects in advanced packaging, warpage is a main reliability concern and may degrade system performance. We present a novel transformer-based encoding scheme to learn node and edge representations, followed by parallel decoding and warpage-aware legalization to jointly minimize die displacement and warpage. Experimental results show that our algorithm improves warpage by 9.9% and wirelength by 8.3% on average, compared with the state-of-the-art work.

This paper presents the first performance-driven pre-assignment routing algorithm for high-speed package designs. The proposed algorithm guarantees the minimum critical path length while preventing wire crossings within a single metal layer. A novel dynamic programming-based method is introduced to efficiently generate a high-quality baseline routing solution, allowing early termination in the subsequent search stage. Then, an efficient search-based method with effective pruning techniques is developed to optimally arrange all nets’ physical routing order, ensuring the minimum critical path length while avoiding suboptimal search branches. The proposed algorithm achieves a 32.9% reduction in the critical path length with only a 0.6% increase in the total path length compared with the previous work across five industrial designs. Furthermore, the proposed search-based method completes the largest design with more than 1000 nets in less than 1.6 seconds, delivering a 5000× speedup over exhaustive branch-and-bound methods while preserving optimality.

Global routing is a critical stage in the VLSI design flow, aiming to provide a robust guide for detailed routing and serve as early design feedback for placement. Many approaches have leveraged GPU parallelization to achieve significant acceleration. However, with the fast-growing complexity of modern large-scale designs, recent GPU-accelerated maze routing algorithms, driven by the sweep operation, struggle to find solutions efficiently with limited GPU memory resources. In order to address this issue, this paper proposes a scalable, GPU-friendly sweep-based maze routing that requires significantly less memory and fewer kernel function calls while accelerating overall runtime. We introduce a sweep-sharing technique that allows multiple nets to be routed simultaneously within a single sweeping process, substantially reducing memory consumption and kernel launching overhead. We further propose an edge-level rip-up-andreroute technique that selectively reroutes only overflowed segments, preserving feasible parts of the solution to reduce runtime substantially. Experimental results on the latest ISPD’24 Contest benchmarks demonstrate that our GPUfriendly maze routing with sweep sharing can significantly improve the efficiency of the state-of-the-art GPU-accelerated maze router.

Escape routing is a critical problem in PCB routing, and its quality greatly affects the PCB design cost. Unlike the traditional escape routing that works mainly for the BGA package with unique line width and space, this paper presents a high-performance escape routing algorithm to handle problems with variable design rules and manual constraints, including variable line widths/spaces, the neck mode of wires, and the pad entry for differential pairs. We first propose a novel obstacle-avoiding method to project pins to the boundary and construct a channel projection graph. We then construct a bi-projection graph and propose a matching-based hierarchical sequencing algorithm to consider manual constraints. We perform global routing for each pin/differential pair by congestion-avoiding path initialization and rip-up and reroute path optimization. Finally, we complete detailed routing in every face, ensuring the wire angle and pad entry constraints. Experimental results show that our algorithm can achieve 100% routability without any design rule violation for all given industrial PCB instances, while two state-of-the-art routers cannot complete routing.

Editor's notes: This article explores heterogeneous integration as a vital approach to overcome the limitations of CMOS scaling by combining multiple distinct dies into a single package or system, reviewing recent technological advances and design strategies while outlining future research directions. -Jorg Henkel, Vice-President of Publications, IEEE CEDA -L. Miguel Silveira, President, IEEE CEDA

In modern printed circuit board (PCB) designs, the increasing complexity poses more challenges for automatic placement. Existing PCB placement methods cannot handle complex constraints with heterogeneous, irregular-shaped, and any-oriented components for double-sided PCB designs well. This paper proposes the first constraint graph-based legalization approach for these constraints. We use a slicing technique to model a component more accurately with a set of rectangles instead of resorting to the naive bounding box approximation. Unlike the commonly used linear programming method for macro placement in integrated circuit (IC) designs, we employ a mixed integer linear programming (MILP) formulation to effectively expand the solution space for heterogeneous, irregular-shaped, and any-oriented components, particularly with high-density designs. Experimental results demonstrate the effectiveness and the robustness of our work.

The fast-growing complexity of VLSI circuits with non-integer multiple-cell-height (NIMCH) standard cells poses new challenges for timing-aware node remapping. The existing remapping flow suffers from significant computational overhead due to exhaustive enumeration of all node-to-gate mapping combinations, including nodes and their fanin nodes. To remedy this inefficiency, we propose a novel NIMCH node remapping flow consisting of the following two schemes: a parallel longest-path-first scheme and an iterative minimum-slack-first scheme. Both schemes prioritize timing-critical nodes to reduce runtime. Moreover, the first scheme enables parallel execution, substantially accelerating the remapping process. Experimental results show that our proposed method achieves an average runtime speedup of 5.58X compared to the state-of-the-art approach, while preserving placement quality. The improved efficiency and scalability of our flow make it well-suited for large-scale physical design applications where rapid timing closure is essential.

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for system-on-chip designs. Recent work in the WRONoC topology designs mainly utilizes crossing switching elements (CSEs) as switching mechanisms on predefined templates. However, using CSEs incurs more microring resonator (MRR) usage and waveguide crossings than parallel switching elements (PSEs), and their predefined templates constrain the solution spaces. To remedy these disadvantages, we propose a fully automated topology design flow that utilizes PSE structures to reduce MRR usage and waveguide crossings. Our add-drop filter sequence model expands the solution space and leverages the advantage of the crossing-free PSE structure. With the sequence model, we also derive lower bounds of the MRR usage and the maximum insertion loss for the topology. For full-connectivity topologies, our proposed flow guarantees optimal (minimum) MRR usage. Our fixed-node crossing-aware edge routing effectively minimizes waveguide crossings, and our A*-search preserves the admissibility property and guarantees an optimal routing solution. Besides, our design flow thoroughly considers the information from the physical layout. Experimental results show that our design substantially outperforms state-of-the-art works on customized designs.