A wideband track-and-hold amplifier (THA) for high-speed sampling in analog front-end (AFE) is designed and fabricated in a 0.8-& micro;m indium phosphide (InP) process with 165 GHz cut-off frequency (fT). Broadband operation is achieved using an enhanced degenerated Darlington fT-doubler buffer, which is first used in the switched-emitter follower (SEF) sampling architecture. Compared with the traditional fT-doubler structures, the enhanced cascode Darlington fT-doubler structure reduces the "VCE mismatch" between the amplifying transistors. Moreover, it can also achieve higher gain more easily, and provide higher VCE for amplifying transistors, which represents higher fT,peak performance. Benefiting from the proposed Darlington fT-doubler buffer, the driving capacity of the input stage is also improved. Besides, capacitive/resistive degeneration is introduced to provide higher bandwidth, which generates a zero to cancel the dominant pole of the THA. Moreover, transmission lines (TLs) at the emitter of cascode stages are adopted to reduce the loss of the sampled signals and the drop in the circuit bandwidth. By these methods, the bandwidth is significantly enhanced. The measurement results show that the THA achieves a bandwidth from DC to 29.8 GHz, exhibiting a 0.181-fT bandwidth utilization. At 25-GSa/s sampling rate, a total harmonic distortion (THD) of less than-35 dBc and the maximum spurious-free dynamic range (SFDR) of 52.3 dB are tested. The power consumption of the THA is only 672 mW, exhibiting a competitive performance compared with other advanced THAs.

A novel and accurate design process for terahertz monolithic integrated circuit(TMIC)is proposed in this work.This process encompasses an indium phosphide(InP)high electron mobility transistor(HEMT)small-signal model and an amplifier using three-dimensional electromagnetic(3D-EM)simulation technology.For device modeling,equivalent parasitic parameters of InP HEMT are extracted through 3D-EM simulation by constructing the physical model of InP HEMT and its equivalent circuit.For circuit design,a full 3D-EM layout environment is implemented,innovatively incorporating a stability cell structure to more accurately predict the impact of high-frequency passive parasitics on transistor performance.In the stability cell,source degeneration and resistor-cap-acitor(RC)network techniques are implemented through 3D-EM simulation,and then combined with the afore-mentioned precise small-signal model,which enables the analysis of the comprehensive impacts of passive struc-tures on both cell stability and maximum available gain(Maxgain).Finally,input and output matching for the stability cell is achieved via 3D-EM simulation,resulting in a complete 3D model of chip.To validate the pro-posed TMIC design process,an 110-140 GHz three-stage small-signal amplifier was designed and measured.The maximum deviation between the simulation and measurement gains is only 2.3 dB across the band,representing an improvement of 1-2 dB over conventional approaches,thereby validating the methodology's accuracy.

In this work, 100 nm gate-length InP-based high electron mobility transistors (HEMTs) with a composite InGaAs/InAs/InGaAs channel are fabricated. DC measurements indicate that the InAs channel enhances transconductance but shifts the peak point toward lower V(gs )under high V-ds bias. Peak separation analysis reveals the DC transconductance curve is composed of two components: the gate-controlled transconductance and the impact-ionization-induced additional transconductance. Further analysis demonstrates that the anomalous shift originates from the channel impact ionization intensity variation, which is caused by changes in the gate-drain electric field rather than the carrier density in the channel. Two additional current sources are introduced in the small-signal model to characterize the impact-ionization-induced transconductance, and the numerical variation trends of their parameters are consistent with the peak separation results, which validate the mechanism's correctness. RF measurements confirm that the DC transconductance enhancement does not effectively improve RF characteristics, which is attributed to the ionization-induced transconductance having a time constant significantly larger than that of conventional transconductance components. These findings provide a theoretical foundation for controlling the impact-ionization.

A compact fundamental 140 GHz mixer using our in-house 80 nm T-gate InP HEMT process is designed, fabricated and characterized. A compact resistive topology is designed to enable low power consumption, high conversion gain and high integration. Measurement results show a maximum conversion gain of-9 dB and an IF bandwidth of 15 GHz within the 130 GHz-150 GHz range under a LO power of-1 dBm. The proposed resistive mixer features a compact size of 0.63 mm x 0.9 mm and can be fabricated with InP HEMT LNA on the same wafer. The results demonstrate that the mixer is well suited for integrated terahertz receiver front-ends.

This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) analog-to-digital converter (ADC)-digital signal processing (DSP)-based retimer transceiver for reaching-distance extension. An injection-locked oscillator (ILO)-based jitter-filtering clocking scheme with relaxed bandwidth limitation and low-power consumption is proposed to obtain synchronous low-jitter clocks. The transmitter (TX) utilizes an internal feed-forward equalizer (FFE) cascaded with a forward-coupling pad driver to improve the output inter-symbol interference (ISI) jitter, and a timing-optimized 4:1 multiplexer (MUX) to reduce the serialization jitter. The receiver (RX) combines a flexible continuous-time linear equalizer (CTLE), a signal-to-noise ratio (SNR)-optimized ADC with 8-bit quantization, and a high-resolution digital equalization to further minimize the bit-error rate (BER). Fabricated in a 28-nm CMOS process, the prototype transceiver achieves 1E-12 raw BER at 112 Gb/s while compensating 31.2-dB channel loss. The clock network delivers a rms recovered clock jitter of 252 fs and a power efficiency of 0.56 pJ/bit, which outperforms other state-of-the-art works.

In this paper, a linear optimization method(LOM) for the design of terahertz circuits is presented, aimed at enhancing the simulation efficacy and reducing the time of the circuit design workflow. This method en & hybull; ables the rapid determination of optimal embedding impedance for diodes across a specific bandwidth to achieve maximum efficiency through harmonic balance simulations. By optimizing the linear matching circuit with the op & hybull; timal embedding impedance, the method effectively segregates the simulation of the linear segments from the non & hybull; linear segments in the frequency multiplier circuit, substantially improving the speed of simulations. The design of on-chip linear matching circuits adopts a modular circuit design strategy, incorporating fixed load resistors to simplify the matching challenge. Utilizing this approach, a 340 GHz frequency doubler was developed and mea & hybull; sured. The results demonstrate that, across a bandwidth of 330 GHz to 342 GHz, the efficiency of the doubler re & hybull; mains above 10%, with an input power ranging from 98 mW to 141mW and an output power exceeding 13 mW. Notably, at an input power of 141 mW, a peak output power of 21. 8 mW was achieved at 334 GHz, correspond & hybull; ing to an efficiency of 15. 8%.

This article presents a 100 Gb/s four-level pulse amplitude modulation (PAM4) analog front-end (AFE) implemented in TSMC's 28-nm CMOS process. The continuous-time linear equalizer (CTLE) employs the transconductance (GM) stage for mid-frequency (MF) peaking, while leveraging the transimpedance (TIA) stage to produce high-frequency (HF) peaking. This allows the HF peak frequency to remain constant as the boost range is adjusted. While the variable gain amplifier (VGA) employs shunt inductive peaking and feedforward technique to extend bandwidth. Both CTLE and VGA use complementary structures to improve linearity. Frequency response tests show the AFE has a 31 GHz peak frequency and a 33.1 dB gain boost. Eye diagram measurements confirm it can open eyes for 100 Gb/s PAM4 signals.

The edge electric field effect of the Schottky junction impacts the diode performance, limiting their application in terahertz frequency multiplier circuits. To address this problem, this paper presents a novel GaAs Schottky barrier diode(SBD) with a vertical sidewall epitaxial profile, which is fabricated by Inductively Coupled Plasmadry(ICP) dry etching. Electromagnetic simulation of the two types of SBD is also carried out to investigate the effect of structural changes on the parasitic effects. Compared to the normal structure SBD, the new design increases the reverse breakdown voltage from-7.5V to-8.4V and reduces the coupling capacitance between the metal finger and the mesa from 4.9 fF to 1.7 fF. A 170 GHz frequency doubler based on this diode demonstrates a maximum frequency doubling efficiency improvement of 4.9% over normal structure SBD, which validates the effectiveness of the SBD with a vertical sidewall epitaxial structure in enhancing the performance of frequency multipliers.

A novel 5 GS/s highly linear voltage-scalable voltage-to-time converter (VTC) has been presented for the time-domain (TD) ADCs. The proposed VTC employs an innovative sample-and-hold (S/H) network to scale the sampled voltage, extending the input voltage range while overcoming the trade-off between linearity and input range that has been a limitation of conventional VTCs. In addition, this work introduces an enhanced bootstrapped switch to improve linearity when handling high-frequency input signals. The proposed VTC is designed in the 28 nm CMOS process, occupying an area of 972 mu m2$\mu{\rm m}<^>2$. Post-layout simulation results demonstrate that, with an input voltage of 1.4 Vpp,diff${\rm V}_{\text{pp}, \text{diff}}$, the VTC achieves a total harmonic distortion (THD) of -62.9 dB and a spurious-free dynamic range (SFDR) of 65.5 dB for Nyquist input, while consuming only 1.92 mW of power.

Post-oxidation annealing (POA) is widely employed in academic research as well as in mass production to improve the properties of SiC MOS devices. We investigate the effect of sequential annealing in NO and wet-O2 on the interfacial properties and reliability of 4H-SiC MOS capacitors. Compared with SiC MOS capacitors with normal NO annealing, the samples with NO and wet annealing show almost identical interface state density, near-interface trap density and F-N effective barrier height. Regarding the breakdown characteristics, the charge-to-breakdown (QBD) of sample NO/wet is increased by two times compared to sample NO at cumulative failure probability F = 63.2%. Moreover, XPS analysis results confirm that sequential annealing can reduce the interface states and improve the oxide reliability by eliminating Si-related SiOxCy defects and carbon-related defects. The subsequent wet annealing can not only annihilate oxygen vacancies which are generated by additional oxidation after NO POA but also suppress the deterioration of bulk SiO2 quality to further improve the gate oxide reliability of SiC MOS structures. These results will be useful for improved control of interface state passivation technologies and for further optimization of the properties of the SiO2/4H-SiC interface.

In this paper, the effects of 2 MeV-proton irradiation on the electrical characteristics of InP/InGaAs double heterojunction bipolar transistors (DHBTs) are investigated. The device characteristics suddenly degraded for proton fluences exceeding $1\times 10{<^>{{13}}}$ cm-2 and almost functionally failed for proton fluences reaches $1\times 10{<^>{{14}}}$ cm ${}<^>{-}2 $ . The increase in base current is directly responsible for the degradation of current gain. It was demonstrated that the reciprocal gain of irradiated InP/InGaAs DHBTs exhibits an exponential relationship with proton fluence over a broader fluence range below $5\times 10{<^>{{13}}}$ cm ${}<^>{-}2 $ , rather than a linear relationship as described by the Messenger-Spratt equation. The analysis of base current components and micro-Raman spectrums indicates that the electrostatic-potential modulation effect of irradiated defects as charged centers on the BE junction is the main cause of gain degradation. Furthermore, a comparison with irradiation effects of other bipolar transistors enhances our understanding of the varied impact of radiation-induced defects on the gain degradation across different transistor architectures.

Radiation experiments of 560 keV, 2 MeV, and 10 MeV proton have been performed on InP-based High Electron Mobility Transistors (HEMTs), the damage mechanisms and damage equivalence are systematically studied. The irradiated devices have exhibited the reduction of transconductance, the positive shift of threshold voltage, and the reduction in drain-source current. Nonionizing energy loss (NIEL) was calculated to investigate the relationship between the degradation of the device and proton energy, but the damage factors of the devices do not exhibit a perfect linear relationship with NIEL across all the energies. The deviation mainly lies in the stopping power of the target material for incident protons. An improved NIEL calculation method is proposed based on Geant4 simulation software, which eliminates the influence of stopping power. And thus, the equivalence of displacement damage in InP-based HEMTs has been constructed among 560 keV, 2 MeV, and 10 MeV proton irradiation.

Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device's performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device's RON is 410 Omega.mu m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device's maximum oscillation frequency(f(max)) by reducing the parasitic capacitance. At 7 K, the device's fmax reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the Si3N4 passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device's cryogenic performance.

In this work, we investigate the impact of the whole small recess offset on DC and RF characteristics of InP high electron mobility transistors (HEMTs).Lg = 80 nm HEMTs are fabricated with a double-recessed gate process. We focus on their DC and RF responses, including the maximum transconductance (g(m_max)), ON-resis & hybull;tance (R-ON), current-gain cutoff frequency (f(T)), and maximum oscillation frequency (f(max)). The devices have al & hybull;most same RON. The g(m_max) improves as the whole small recess moves toward the source. However, a small gate to source capacitance (C-gs) and a small drain output conductance (g(ds)) lead to the largest f(T), although the whole small gate recess moves toward the drain leads to the smaller g(m_max). According to the small-signal modeling, the device with the whole small recess toward drain exhibits an excellent RF characteristics, such as f(T) = 372 GHz and fmax= 394 GHz. This result is achieved by paying attention to adjust resistive and capacitive parasitics, which play a key role in high-frequency response

In this work, a 2 MeV proton irradiation experiment has been carried out on self-fabricated InP/InGaAs heter-ojunction bipolar transistors (HBTs) with fluence of 5 x 1013 H+/cm2 and 1 x 1014 H+/cm2. The degradation and mechanisms have systematically been studied under different bias conditions. The irradiated InP-based HBTs have suffered more sever degradation at low and high bias voltages with larger damage coefficient of current gain (K beta), due to the increased base recombination current and the slacken collector current respectively. Under high injection current densities, the slow-down of collector current and the collapse of current gain (beta) have occurred at increasingly smaller biases as irradiation fluence increases. Consistently, the ideality factor of base current collapses to 1 at high injection current, moreover, the collapse point decreases as fluence increases. The aggravated degradation at high current densities is attributed to the influence of heterojunction barrier effect (HBE) by the structure of the multi-layer collector region. The study would be of great significance for optimizing the device structure and improving the irradiation tolerance.

This letter presents a four-port noise de-embedding procedure for on-wafer microwave measurements based on electromagnetic (EM) simulation. The proposed de-embedding procedure uses EM simulation dummy structures and only one device measurement to eliminate the parasitic effects from the probe pads and metal interconnects of a device under test (DUT). This method can generate intrinsic noise characteristics parameters to efficiently and precisely remove the redundant parasitic of the DUTs with various device sizes. The accuracy and feasibility of the noise de-embedding method are verified by comparing the de-embedding results of EM simulation, on-wafer testing, and circuit-model-calculated. Finally, we evaluate the accuracy of the de-embedding approach with the traditional approach and experimental data obtained on InP HEMT.

The research on high power 190 GHz doubler based on the GaAs Schottky diodes is proposed in this paper. The frequency doubler comprises a improved diode configuration that increases the number of anodes by changing the diode arrangement to improve power handling capacity. Electromagnetic and thermal simulation is utilized to demonstrate that the doubler can carry more power. The input power is gradually pumping from 200 mW to 500 mW with an applied DC bias of -15 V. And the peak efficiency of the doubler is measured to be 17%, while the maximum output power is 85 mW at 190 GHz.

The paper investigated the deposition sequence-dependent behavior of Ni (50 nm)/Ti (60 nm)/W (60 nm) and Ni (50 nm)/W (60 nm)/Ti (60 nm) Ohmic contacts on n-type 4H-SiC after annealing at 1050 degrees C for 3 min in Ar atmosphere by in-depth electrical and physical characterization. The contact resistivity of the Ni/Ti/W structure ( 8.43 x 10_6 _ 6 Omega & sdot;cm2) 2 ) was found to be lower than that of the Ni/W/Ti structure ( 21.9 x 10_6 _ 6 Omega & sdot;cm2). 2 ). For the Ni/W/Ti structure, the W layer closer to the contact interface led to an increase in the preferred orientation degree of the delta-Ni2Si 2 Si (220) plane at the interface, favoring a lower contact resistivity according to previous studies. However, the content and interfacial coverage of delta-Ni2Si 2 Si is reduced by the WxNiyC x Ni y C phase and the interfacial strain/stress is greatly increased by the WxNiyC x Ni y C phase as well, which ultimately leads to an increase in the contact resistivity. The larger interfacial strain/stress in the Ni/W/Ti structure also results in a rough surface morphology with more microcracks and a large area of delamination. In addition, the shearing strength of Al wire bonding points on the Ni/W/Ti surface is slightly weaker than that on the Ni/Ti/W surface due to the higher surface roughness. The above experimental findings can provide a guideline for further structural optimization of the 4H-SiC Ohmic contacts.

This paper presents a broadband fully differential amplifier using a 0.8- mu m InP DHBT process, exhibiting a bandwidth exceeding 8 GHz from DC and achieves a differential gain of 14.56 dB, occupying 0.78 mm x 0.7 mm with all pads involved and consuming only 375 mW with a-5 V power supply. The core of the design leverages an operational amplifier with Cherry-Hooper architecture, incorporating global shunt-shunt feedback to ensure high gain linearity across the bandwidth. Notably, the-1 dB bandwidth of this circuit extends up to 5 GHz. Additionally, the design is entirely devoid of inductors, resulting in a consistent gain profile without any significant gain peaking.

AbstractInvestigating the intrinsic properties of the Schottky interface between graphene and 3D bulk silicon is crucial. However, the semiconductor technology introduces extra doping and defects in graphene, which significantly disturbs the property of the graphene‐silicon interface. Here, the interface parameters of graphene/n‐Si heterojunction are derived by the damage‐free Hg‐probe capacitance–voltage measurement. Due to its low‐density states, the Fermi level of graphene can be pushed upward, which results in a lower Schottky barrier height (ΦB0) of Hg/graphene/n‐Si (HGS) heterostructure than that of Hg/n‐Si (HS) structure. Additionally, the series resistance (Rs) of HGS becomes lower than that of HS, which can be attributed to the narrowed depletion layer width (WD) and the decreased interface state density (Nit). Furthermore, the frequency characteristic is also investigated. Because of the weak interface state charge trapping–detrapping process and the decreased Nit at high frequency, electrons will accumulate in graphene, and the Fermi level will be pushed up. Hence, the ΦB0 and Rs will decrease with increasing frequency. This study contributes to a deep understanding of the graphene/silicon heterojunction interfaces, which is crucial for designing and optimizing the new electronic and optoelectronic devices based on 2D/3D heterostructure.