This work investigates the root causes of output voltage (VOUT) degradation in a 40V EDPMOS technology used in mobile power-management ICs (PMICs). By combining device electrical characterization, SCM analysis, and process-module experiments, we identify photoresist-induced implant shadowing in the high voltage N-well (HVNW) formation step as a dominant contributor to VOUT loss. A systematic study of photoresist thickness scaling and implant-angle optimization demonstrates that both thinner photoresist and quadro-angle ion implantation independently and significantly improve HVNW doping uniformity, resulting in increased VOUT.
Strain and defect engineering are widely employed to tune the electronic properties of two-dimensional semiconductors. In reality, both stress and defects coexist; however, their coupled impact remains poorly understood. Here, we present a systematic first-principles study of the interplay between mechanical stress and defect functionalization in monolayer WS2. Uniaxial and biaxial stresses (up to ±2 GPa) are applied to pristine, mono-sulfur vacancy, and Halogen-functionalized WS2 monolayers, including iodine substitution and adsorption of iodine/fluorine. Tensile stress results in significantly stronger electronic modulation, with a reduction in bandgap of ∼30%, compared to a ∼7.5% increase under compression. For both uniaxial and biaxial stresses, the doping polarity remains invariant, with substituted iodine exhibiting n-type behavior and adsorbed halogens inducing p-type characteristics. The effective doping strength is strongly stress-dependent, as evidenced by band-edge shifts and charge redistribution. Uniaxial tensile stress enhances donor activation for both halogen-absorbed and substituted WS2. Similarly, for sulfur vacancies, uniaxial tensile stress breaks the symmetry and splits W-d derived defect states, shifting them towards the conduction band and enhancing p-type character. These results reveal stress as an efficient amplifier of defect-induced electronic modulation and establish stress–defect co-engineering as a practical strategy to modulate carrier type, Fermi-level alignment, and transport properties in WS2 for next-generation nanoelectronics applications.
Near-infrared (NIR) sensors are becoming increasingly important in diverse fields, including autonomous driving, biomedical imaging, and nondestructive food analysis. However, the intrinsic absorption limit of Si, determined by its ~1.1 eV bandgap, restricts its detection range in the long-wavelength NIR region. In this study, we demonstrate that the cutoff wavelength of Si-based photodetectors can be extended by employing heavily doped (low-resistivity) degenerate Si in a metal-oxide semiconductor (MOS) field-effect transistor-type device architecture. Devices with channel lengths ranging 5–50 μm were fabricated on both degenerate (0.015 Ω·cm, 4.3 × 10¹⁸ cm–³) and standard-resistivity (2 Ω·cm, 7.0 × 10¹⁵ cm–³) Si substrates to investigate the influence of degenerate semiconductor effects on NIR photodetection characteristics. The standard-resistivity (2 Ω·cm) devices exhibited photoresponses up to approximately 1100 nm, whereas the degenerate Si devices showed a distinct extension of the detectable wavelength range to ~1200 nm. This extension beyond the intrinsic Si absorption limit is primarily attributed to bandgap narrowing induced by heavy doping. The threshold voltage shifted from –0.5 V in the 2 Ω·cm devices to 2.2 V in the degenerate devices, while the dark current increased from 1.2 × 10–10 A to 2.5 × 10–10 A, reflecting the influence of the elevated substrate doping concentration on channel formation. At 1200 nm, the degenerate Si devices exhibited enhanced photoresponse characteristics, achieving a peak detectivity of 6.1 × 106 Jones, compared with 4.7 × 105 Jones for the standard-resistivity devices. These results demonstrate that degenerate semiconductor engineering provides a CMOS-compatible approach for extending the detectable wavelength range and enhancing NIR photoresponse beyond the intrinsic absorption limit of Si.
Continuous electrocardiogram (ECG) monitoring enabled by wearable and implantable bioelectronic devices generates dense physiological data streams that must be interpreted under strict energy, communication, and latency constraints. This study presents a resource-aware hierarchical ECG monitoring framework that combines lightweight device-level screening with selective Large Language Model (LLM)-style short-horizon waveform forecasting. The device-side layer is formulated as patient-baseline-aware stability screening: baseline-consistent windows remain under local monitoring or summary logging, whereas windows showing rhythm/event irregularity or morphology deviation are escalated for off-device analysis. In a 15-record MIT-BIH Arrhythmia Database evaluation, the primary operating point achieved 95.2% sensitivity with a 4.8% false-negative rate while forwarding 40.9% of windows, corresponding to a 59.1% reduction in forwarded-window volume relative to always escalating all windows. A safety-stressed operating point further reduced the false-negative rate to 1.6% at the cost of a higher forwarding rate. The measured escalation rates were then used to estimate communication load and wireless transmission-energy components. For the forecasting layer, the study evaluates Time-LLM-style configurations using frozen GPT-2 Small and DeepSeek-Coder-1.3B-Base backbones, together with Persistence and TCN baselines on representative records. Full context-enhanced Time-LLM variants generally improved over Patch-only variants and remained competitive with direct baselines, although the gains were metric- and beat-type-dependent. The results support patient-baseline-aware selective ECG forwarding and selective off-device waveform modeling for resource-constrained bioelectronic monitoring, without treating short-horizon forecasting as clinical diagnosis.
In this work, we develop a SPICE-compatible compact model for a fabricated dual-gate positive feedback field-effect transistor (FBFET) based on measured device characteristics. The model parameters are quantitatively extracted to reproduce the DC transfer characteristics, temperature-dependent switching behavior, and transient responses of the device. The proposed framework captures the charge injection–accumulation–positive feedback mechanism responsible for abrupt switching and the characteristic delay associated with charge accumulation in the floating body. Temperature-dependent variations in threshold voltage and drain current are incorporated using experimentally calibrated scaling parameters. In addition, an ONO-based charge-trapping module is incorporated using TCAD-extracted memory-window characteristics as an exploratory extension toward charge-trap memory and processing-in-memory applications. Finally, the circuit-level applicability of the proposed model is validated by comparing the measured and SPICE-simulated responses of a fabricated FBFET-based hybrid inverter. The model successfully reproduces the inverter operation and the drain-voltage-dependent pull-down limitation of the FBFET, demonstrating its practical applicability to circuit-level analysis.
For the first time, an InAlGaN/GaN MISHEMT integrated with a tri-gate architecture and a hybrid ferroelectric charge trap gate (FEG) stack is demonstrated in this study. The device yields a significant positive threshold voltage shift (ΔVth) of 19 V owing to the high effectiveness of these two techniques in depleting the 2DEG channel. Furthermore, the use of high-quality atomic layer deposition (ALD) dielectric films and TMAH surface modification ensures a high Ion/Ioff ratio of 1010 and remarkably low gate leakage current of 10-6 mA/mm. Compared to a conventional AlGaN/GaN epilayer with same process design, the proposed device shows higher output drain current (IDS,max = 1265 mA/mm) and lower on resistance (Ron = 4.6 Ω·mm). Temperature-dependent IGS-VGS characteristics and Frequency-dispersion capacitance-voltage measurements were also conducted to investigate the surface trap states. Time-dependent dielectric breakdown (TDDB) lifetime test predicted that the proposed device exhibits a reliable operating lifetime exceeding 10 years at 10.97 V.
Accurate characterization of memory reliability in two-terminal devices remains a challenge due to the slow sweep speeds of traditional capacitance-voltage (CV) measurement systems like LCR meters. These slow measurements often introduce read-disturb effects, making it difficult to capture the true memory state. Earlier developed fast-CV techniques suffer from limited voltage sweep ranges and lack of high-voltage program/erase functionality. In this work, a custom-built high-speed CV (HSCV) measurement system is designed, capable of capturing complete CV curves within 10 μs for reliability characterization of two terminal memory devices. The system uses microcontroller and Op-amp based triangular waveform generator, along with integrated relay-based high-voltage switching to perform program, erase, and read operations without disturbing the device. It is deployed to study reliability of memory devices based on CdTe nanoparticles embedded between ALPO dielectric layers. Under a ±12 V P/E pulse, these devices exhibit a large memory window of 4.8 V, indicating strong charge trapping. Endurance testing using the HSCV system up to 10,000 cycles shows a stable memory window of 5.5 V. Retention measurements performed up to 10,000 seconds reveal a memory window reduction from 2.8 V to 2.1 V, confirming good long-term charge retention. These results show that the HSCV system provides a low-cost and read-disturb-free platform for accurately capturing charge-trapping dynamics and flatband voltage shifts. Although the technique is demonstrated here on CdTe/ALPO nanoparticle-based memory devices, the system is universal and can be applied to a wide range of two-terminal charge-trap memory devices.
Conventional emission driver circuits in organic light-emitting diode (OLED) displays typically rely on periodic boosting of internal nodes to maintain stable output voltages, which inevitably accompanies periodic charging and discharging of internal capacitors. This not only leads to high dynamic power consumption but also increases circuit complexity due to the boosting structures. To solve this issue, we propose a novel emission driver circuit that employs charging-delay-based bootstrapping with complementary dual-input and output signals. The charging-delay bootstrapping method eliminates the need for periodic charging and discharging of the internal capacitor, thereby reducing dynamic power consumption, and the dual-input scheme simplifies the overall circuit structure. SPICE simulation results confirm that the proposed circuit maintains stable output voltage waveforms under various pulse-width-modulation (PWM) driving conditions of the OLED display while achieving up to 64.4% reduction of power consumption compared with conventional circuits. Furthermore, measurement results from fabricated test samples confirm that the circuit maintains stable output voltage waveforms even after 300 hours of continuous operation.
In this paper, a symmetric multi-stub resonator (SMSR) is proposed for the design of millimeter-wave on-chip bandpass filters (BPFs) with wide bandwidths, low insertion losses (ILs), and compact sizes. The multimode resonant characteristics are investigated and can be adjusted by varying the dimensions of the SMSR, enabling flexible control of the filtering responses. To validate the proposed idea, two BPF prototypes are designed and fabricated using a 0.25-μm gallium arsenide (GaAs) process. The measured results show that the fabricated devices operate at center frequencies of 51.3 GHz and 52 GHz, with 3-dB fractional bandwidths of 24.8% and 25.5%, and minimum in-band ILs of 1.07 dB and 1.1 dB, respectively. Excluding the G-S-G pads, the two proposed BPFs occupy core areas of only 0.063 λ0 × 0.042 λ0 and 0.063 λ0 × 0.055 λ0, respectively.
In this paper, we proposed an ultra low-power scan driver circuit based on amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) for active-matrix organic light-emitting diode (AMOLED) displays. To achieve low-power consumption without additional control signals or power sources, the proposed scan driver employed a single negative power source and a series-connected two-transistor (STT) structure, enabling stable operation even in depletion mode under a ΔVTH of –1.2 V. Furthermore, extra clock signals with a frequency equal to the frame rate were applied to the pull-down unit to suppress circuit malfunctions caused by threshold voltage shifts in a-IGZO TFTs. The fabricated single-stage scan driver was designed with an area of 402 μm ´ 40 μm, and experimentally confirmed stable sequential shifting operation across a wide range of clock frequencies from 64.8 kHz up to 194.4 kHz. The simulated power consumption of the proposed scan driver with 2160 stages was calculated as 19.5 mW at the frame rate of 120 Hz.
Cryogenic non-volatile memory technologies are crucial for realizing energy-efficient and scalable quantum computing systems. Ferroelectric capacitors (FeCAPs) are promising candidates; however, conventional readout relies on polarization switching, resulting in destructive operation. In this work, we demonstrate the cryogenic implementation of non-destructive capacitive readout (NDRO) in conventional Hf0.5Zr0.5O2-based capacitors down to 10 K. By exploiting the capacitance difference between polarization states, stable readout at Vread = 0 V is achieved without perturbing the stored state. The devices exhibit stable retention over 1000 s and low variability across devices and repeated reads at room temperature, 77 K, and 10 K. Multilevel operation is demonstrated at 10 K with multiple distinct capacitance states maintained under NDRO conditions. Endurance measurements at 10 K show clear state separation beyond 107 cycles. Analysis of the temperature-dependent behaviour indicates that imprint-induced asymmetry plays a key role in enabling reliable state discrimination at cryogenic temperatures, despite the reduction in absolute capacitance with decreasing temperature. These results demonstrate the feasibility of NDRO in standard nominally symmetric ferroelectric capacitors at cryogenic temperatures without deliberate interface engineering, highlighting their potential for cryogenic memory and in-memory computing applications.
Implantable neurostimulators are critical for treating neurological disorders and require compact CMOS systems with long-term reliability. Electrostatic discharge (ESD) can damage thin oxide layers in the CMOS and can cause significant damage to systems. Conventional ESD protection circuits, such as clamp-based schemes with implicit or explicit diodes, are practical but require considerable area and complexity. Conversely, simpler protection architectures are more suitable for high-voltage neural interfaces, for which area and robustness are the key requirements. The major challenge is to achieve efficient ESD protection while ensuring operational safety and low layout area. This paper presents a compact back-to-back diode–based ESD protection design for neurostimulators in 65 nm CMOS technology, primarily targeting HBM-level ESD protection. The circuit has also been tested for CDM-level robustness; however, the main focus of this work remains on achieving reliable HBM performance. The proposed back-to-back diode design reduces clamping voltage by ~53% and dynamic resistance by ~89% when compared with implicit clamps while meeting the normal voltage operation range. In addition, the proposed design reduces dynamic resistance by more than 92% compared to the typical foundry design. As a result, ESD protection can be decoupled from stimulator drivers, allowing for more modular and area-efficient H-bridge designs. This simplifies the layout, eliminates the need for clamping transistors, and provides robust bidirectional ESD protection. Our work proposes a scalable ESD strategy appropriate for next-generation implantable SoC-based biomedical devices by addressing electrical and physical constraints.
We demonstrate the high scalability of equivalent oxide thickness (EOT) scaled HfO2-ZrO2-HfO2 (HZH) gate stacks based on FinFETs with a physical gate length $(L_{\mathrm { g}})$ of 25 nm. Benefiting from the ultra-thin 7.1 Å EOT on HZH films after $450~^{\circ }$ C annealing, superior performance, including enhanced driving current $(I_{\mathrm { on}})$ and short channel effect (SCE) immunity, is achieved on HZH-FinFETs and is maintained with $L_{\mathrm { g}}$ scaled to ~25 nm. Compared with traditional HfO2-based FinFETs, a 38% increase in $I_{\mathrm { on}}$ and a 54% improvement in transconductance are observed in HZH-FinFETs with 25 nm $L_{\mathrm { g}}$ . Furthermore, due to the absence of IL scavenging and low interface trap density $(D_{\mathrm { it}})$ in HZH gate stacks, mobility degradation was not observed in the HZH FinFET. Additionally, the HZH gate stack shows a comparable level of TDDB and NBTI reliability to that of $\rm HfO_{\mathrm {2}}$ devices, indicating the great potential of HZH for future advanced node CMOS technology.
With the increasing demand for secure IoT communications, memristor-based true random number generators (TRNGs) provide promising hardware security solutions. Here, a TiN/LiSiOx/Pt memristor array is demonstrated as an intrinsic entropy source for TRNG applications. The device exhibits stochastic resistive switching with intrinsic set and reset transition times of 45 ns and 36 ns, respectively. Based on this device characteristic, a compact TRNG circuit is implemented, achieving a maximum measured end-to-end throughput of 4.5 Mb/s. A 1 Mbit raw bitstream without algorithmic post-processing is directly collected and evaluated using autocorrelation analysis, Hamming analysis, NIST SP 800-22 statistical tests, and NIST SP 800-90B non-IID entropy estimation. The generated random bits achieve a conservative min-entropy of 0.994 bit per raw bit. Furthermore, SHA-256-conditioned random keys generated from the TRNG are applied to AES-128 image encryption, demonstrating effective information concealment and favorable statistical characteristics. These results demonstrate the potential of TiN/LiSiOx/Pt memristors for high-speed and secure cryptographic application.
Silicon spin qubits are a promising platform for large-scale quantum information processing, but operation at elevated temperature requires quantum dots with both large orbital energy spacing and large charging energy. In this work, we theoretically study silicon metal-oxide-semiconductor fintype quantum dots and clarify how fin width and gate length determine these energy scales. Using a self-consistent quantum and semiclassical device-simulation framework, we calculate the orbital spectrum and total capacitance over a range of device dimensions. We find that the orbital energy spacing does not increase monotonically as the structure is narrowed. Instead, it exhibits a maximum at an intermediate fin width. This nonmonotonic behavior originates from a change in the character of the first excited orbital, from excitation along the gate-length direction in narrow fins to excitation across the fin width in wider fins. In contrast, the charging energy increases monotonically as fin width and gate length are reduced. The results show that aggressive isotropic scaling is not the optimal strategy for elevated-temperature qubit design. Rather, co-optimization of fin width and gate length near the orbital crossover region maximizes orbital energy spacing while preserving sufficiently large charging energy.
