Dharani Shankar GCentre for Development of Advanced Computing Secure Hardware and VLSI Design Group, Bangalore, India关注立即认领分享关注立即认领分享基本信息浏览量:0职业迁徙个人简介暂无内容研究兴趣论文共 2 篇作者统计合作学者相似作者按年份排序按引用量排序主题筛选期刊级别筛选合作者筛选合作机构筛选时间引用量主题期刊级别合作者合作机构Design and Analysis of Posit Quire Processing Engine for Neural Network Applications Pranose J Edavoor,Aneesh Raveendran,David Selvakumar,Vivian Desalphine,Dharani Shankar G,Gopal Raut2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID)pp.252-257, (2023)引用1浏览0EIWOS引用10P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic ProcessorSandra Jean,Aneesh Raveendran,A. David Selvakumar, Gagandeep Kaur,Shankar G Dharani,Shashikala Gunderao Pattanshetty,Vivian Desalphine2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded...(2021)引用5浏览0EIWOS引用50作者统计合作学者合作机构D-Core合作者学生导师暂无相似学者,你可以通过学者研究领域进行搜索筛选数据免责声明页面数据均来自互联网公开来源、合作出版商和通过AI技术自动分析结果,我们不对页面数据的有效性、准确性、正确性、可靠性、完整性和及时性做出任何承诺和保证。若有疑问,可以通过电子邮件方式联系我们:report@aminer.cn