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John E. Barth, Jr., received the B.S.E.E. degree from Northeastern University, Boston, MA, in 1987, and the M.S.E.E. degree from National Technological University (NTU), Fort Collins, CO, in 1992.
During his B.S. degree work, he was employed at the Timeplex Development Laboratory, Rochelle Park, NJ, from 1984 to 1985, where he wrote data communications and network monitoring software. He also worked at the IBM Development Laboratory, Essex Junction, VT, in 1986, where he was involved in the design and characterization of the 1-Mb DRAM product. After receiving his B.S. degree, he returned to the IBM Development Laboratory, Essex Junction, VT, during which time he was involved the design of a 16-Mb DRAM product featuring embedded ECC and SRAM cache. Following this, he was involved the array design for the 16/18-Mb DRAM products. In 1994, he started work on wide I/O, high-performance, DRAM macros for embedded general-purpose ASIC applications. Utilization of these macros expanded into network switching and microprocessor caches. He currently has 17 U.S. patents with 13 pending and has co-authored nine IEEE papers.
Mr. Barth received the IEEE Journal of Solid-State Circuits 1989–1990 Best Paper Award for his paper “A 50 ns 16-Mb DRAM with 10 ns data rate and on-chip ECC.” In 2002, he was co-recipient of the ISSCC Beatrice Award for Editorial Excellence for a 144-Mb DRAM targeted for standalone SRAM cache replacement.
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Journal of Low Power Electronics and Applicationsno. 2 (2014): 77-89
Mykhaylo Teplechuk, Anthony Gribben,Christophe Amadi,Dialog Semiconductor,John E Barth,Erik Nelson, Charlie Hwang,Gregory Fredeman,Michael Sperling, A Z Mathews, William Robert Reohr,Kavita Nair,
IBM Journal of Research and Developmentno. 3 (2011): 259-266
mag(2010)
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