Paul S Andry

IBM Research Division, Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, USA|c|

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Papers13 papers

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2.5D and 3D technology challenges and test vehicle demonstrations

John U Knickerbocker,Paul S Andry,Evan G Colgan,Bing Dang,Timothy O Dickson,X Gu,Chuck Haymes,Christopher V Jahnes,Y Liu,J P Maria,R J Polastre,Cornelia K Tsang

Electronic Components and Technology Conference, pp.1068-1076, (2012)

Cited by87EIWOSBibtex

Investigations of Cu bond structures and demonstration of a wafer-level 3D integration scheme with W TSVs

K N Chen,C Cabral,S H Lee,Paul S Andry, Jun Q Lu

VLSI Technology Systems and Applications, pp.162-163, (2010)

Cited by2EIWOSBibtex

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

Andry, P.S.,Tsang, C.K.,Webb, B.C.,Sprogis, E.J.

IBM Journal of Research and Development, no. 6 (2008): 571-581

EIWOSBibtex

Three-dimensional silicon integration

Knickerbocker, J.U.,Andry, P.S.,Dang, B.,Horton, R.R.

IBM Journal of Research and Development, no. 6 (2008): 553-569

Cited by244EIWOSBibtex

3D silicon integration

John U Knickerbocker,Paul S Andry,Bing Dang,R R Horton,Chirag S Patel,R J Polastre, Katsuyuki Sakuma, E Sprogis,Cornelia K Tsang,Bucknell C Webb,S L Wright

Lake Buena Vista, FL, pp.538-543, (2008)

Cited by142EIWOSBibtex

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Sakuma, K.,Andry, P.S.,Tsang, C.K.,Wright, S.L.

IBM Journal of Research and Development, no. 6 (2008): 611-622

EIWOSBibtex

3D chip stacking with C4 technology

Dang, B.,Wright, S.L.,Andry, P.S.,Sprogis, E.J.

IBM Journal of Research and Development, no. 6 (2008): 599-609

EIWOSBibtex

3-D silicon integration and silicon packaging technology using silicon through-vias

John U. Knickerbocker,Chirag S. Patel,Paul S. Andry,Cornelia K. Tsang,L. Paivikki Buchwalter,Edmund J. Sprogis, Hua Gan,Raymond R. Horton,Robert J. Polastre,Steven L. Wright,John M. Cotte

custom integrated circuits conference, no. 8 (2006): 1718-1725

Bibtex

System-on-package (SOP) technology, characterization and applications

John U Knickerbocker,Paul S Andry,L P Buchwalter,Evan G Colgan,John M Cotte,Haitao Gan,R R Horton,Sri M Srijayantha,J H Magerlein,Dennis G Manzer,G Mcvicker,Chirag S Patel

San Diego, CA, pp.415-+, (2006)

Cited by17EIWOSBibtex

Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor

Paul S Andry,L P Buchwalter, Russell A Budd, Thomas Anthony Wassick

(2006)

Cited by30Bibtex

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology

John U. Knickerbocker,Chirag S. Patel,Paul S. Andry,Cornelia K. Tsang,L. Paivikki Buchwalter,Edmund J. Sprogis,Hua Gan,Raymond R. Horton,Robert J. Polastre,Steven L. Wright,Christian D. Schuster,Christian W. Baks

IEEE Custom Integrated Circuits Conference, pp.659-662, (2005)

Cited by28EIWOSBibtex

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Knickerbocker, J.U.,Andry, P.S.,Buchwalter, L.P.,Deutsch, A.

IBM Journal of Research and Development, no. 4 (2005): 725-753

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Paul S AndryBinding

Papers13 papers

Paul S Andry