Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs

Rouwaida Kanj,Rajiv Joshi,Jayakumaran Sivagnaname,JB Kuang,Dhruva Acharyya,Tuyet Nguyen,Chandler McDowell,Sani Nassif

San Jose, CA（2007）

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摘要

We present a critical study of the impact of gate tunneling currents on the yield of a 65nm PD/SOI SRAM cell. Gate-leakage tunneling currents are obtained from hardware measurements. It is shown that the gate-leakage impact on the cell yield can be non-monotonic, and is appreciable even for non-defective devices. It is also shown that further design optimizations such as the operating voltage or bitline loading can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield, and threshold voltage variations to model random fluctuation effects are extrapolated from hardware.

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关键词

bitline loading,gate-leakage tunneling current,threshold voltage variation,soi sram cell,gate-leakage impact,gate leakage effects,soi sram designs,design considerations,mixture importance sampling,cell yield,hardware measurement,critical study,operating voltage,fluctuations,importance sampling,soi,design optimization,monte carlo methods,silicon on insulator,threshold voltage,integrated circuit design,hardware,tunneling

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